ST10R272L - POWER REDUCTION MODES
302/320
The table below summarizes the state of all ST10R272L output pins during idle and power
down mode
.
Output Pin(s)
Idle Mode
Power Down Mode
ALE
Low
Low
RD, WR
High
High
CLKOUT
Active
High
RSTOUT
1
1.
High if EINIT was executed before entering Idle or Power Down mode, Low otherwise.
1
P0L
Floating
Floating
P0H
A15...A8
2
/ Float
2.
For multiplexed buses with 8-bit data bus.
A15...A8
2
/ Float
PORT1
Last Address
3
/Port Latch Data
3.
For demultiplexed buses.
Last Address
3
/Port Latch Data
Port 4
Port Latch Data/Last segment
Port Latch Data/Last segment
BHE
Last value
Last value
HLDA
Last value
Last value
BREQ
High
High
CSx
Last value
4
4.
The CS signal that corresponds to the last address remains active (low), all other enabled
CS signals remain inactive (high).
Last value
4
Other Port Output
Pins
Port Latch Data / Alternate Function
Port Latch Data / Alternate Function
Table 48 Output pin status during idle and power down modes
