ST10R272L - INTERRUPT AND TRAP FUNCTIONS
105/320
Note
Refer to “Interrupt control registers” on page 86 for an explanation of the control
fields.
6.9 Traps
6.9.1
Software traps
Software Traps can be performed from any vector location between 00’0000h and 00’01FCh.
A service routine entered via a software TRAP instruction, is always executed on the current
CPU priority level (indicated in bit field ILVL in register PSW). This means that routines
entered by the software TRAP instruction can be interrupted by all Hardware Traps or higher
level interrupt requests.
Executing a TRAP instruction causes a similar effect to an interrupt at the same vector. PSW,
CSP (in segmentation mode) and IP are pushed on the internal system stack and a jump is
taken to the specified vector location. When segmentation is enabled and a trap is executed,
the CSP for the trap service routine is set to code segment 0. No Interrupt Request Flags are
affected by the TRAP instruction. The interrupt service routine called by a TRAP instruction
must be terminated with a RETI (return from interrupt) instruction, to ensure correct
operation.
Note
The CPU level in the PSW register is not modified by the TRAP instruction, so the
service routine is executed on the same priority level from which it was invoked.
Therefore, the service routine entered by the TRAP instruction can be interrupted
by other traps or higher priority interrupts, other than when triggered by a Hardware
Trap.
6.9.2
Hardware traps
Exceptions or error conditions that arise during run-time are called Hardware Traps.
Hardware Traps cause immediate non-maskable system reaction, similar to a standard
interrupt service (branching to a dedicated vector table location). The occurrence of a
Hardware Trap is additionally signified by an individual bit in the trap flag register (TFR).
Except when another higher prioritized trap service is in progress, a Hardware Trap will
interrupt any actual program execution. In turn, Hardware Trap services can not normally be
interrupted by standard or PEC interrupts. The following table shows all of the possible
exceptions or error conditions that can arise during run-time:
Exception Condition
Trap Flag
Trap Vector
Vector
Location
Trap
Number
Trap
Priority
Reset Functions:
Table 20 Exceptions or error conditions
