ST10R272L - EXTERNAL BUS INTERFACE
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EXTERNAL BUS INTERFACE
Although the ST10R272L provides a powerful set of on-chip peripherals and on-chip RAM
areas, these internal units only cover a small fraction of its address space of up to 16 MByte.
The external bus interface is used to access external peripherals and additional volatile and
non-volatile memory.
Accesses to external memory or peripherals are executed by the integrated External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes. The function
of the EBC is controlled via the SYSCON register and the BUSCONx and ADDRSELx
registers. The BUSCONx registers specify the external bus cycles in terms of address (mux/
demux), data (16-bit/8-bit), chip selects and length (waitstates / READY control / ALE / RW
delay). These parameters are used for accesses within a specific address area which is
defined via the corresponding register ADDRSELx.
The four pairs BUSCON1/ADDRSEL1...BUSCON4/ADDRSEL4 are used to define four
independent address windows, while all external accesses outside these windows are
controlled by the BUSCON0 register.
Figure 51 SFRs and port pins associated with the external bus interface
P0L/P0H
PORT0 Data Registers
P1L/P1H
PORT1 Data Registers
DP3
Port 3 Direction Control Register
P3
Port 3 Data Register
P4
Port 4 Data Register
ODP6
Port 6 Open Drain Control Register
DP6
Port 6 Direction Control Register
P6
Port 6 Data Register
PORT0
EA
PORT1
RSTIN
ALE
READY
RD
WR/WRL
BHE/WRH
BUSCON3
BUSCON0
BUSCON1
BUSCON2
ADDRSEL4
P0L / P0H
P4
P6
ADDRSEL1
ODP6E
SYSCON
Control Registers
P1L / P1H
BUSCON4
ADDRSEL2
RP0H
DP6
DP3
P3
ADDRSEL3
ADDRSELx
Address Range Select Register 1...4
BUSCONx
Bus Mode Control Register 0...4
SYSCON
System Control Register
RP0H
Port P0H Reset Configuration Register
