ST10R272L - GENERAL PURPOSE TIMER UNITS
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Timer 6 in gated timer mode
Gated timer mode for the core timer T6 is selected by setting bit field T6M in register T6CON
to ‘010
B
’ or ‘011
B
’. Bit T6M.0 (T6CON.3) selects the active level of the gate input. In gated
timer mode the same options for the input frequency as for the timer mode are available.
However, the input clock to the timer in this mode is gated by the external input pin T6IN
(Timer T6 External Input), which is an alternate function of P5.12.
If T6M.0=‘0’, the timer is enabled when T6IN shows a low level. A high level at this pin stops
the timer. If T6M.0=‘1’, pin T6IN must have a high level in order to enable the timer. In
addition, the timer can be turned on or off by software using bit T6R. The timer will only run,
if T6R=‘1’ and the gate is active. It will stop, if either T6R=‘0’ or the gate is inactive.
Note
A transition of the gate signal at pin T6IN does not cause an interrupt request.
Timer 6 in counter mode
Counter mode for the core timer T6 is selected by setting bit field T6M in register T6CON to
‘001
B
’. In counter mode timer T6 is clocked by a transition at the external input pin T6IN,
which is an alternate function of P5.12. The event causing an increment or decrement of the
Figure 85 Block diagram of core timer T6 in gated timer mode
T6IN = P5.12
T6EUD = P5.10
T6OUT = P3.1
x = 6
