ST10R272L - SYSTEM RESET
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15.1
Asynchronous hardware reset
Asynchronous reset does not required a stabilized clock signal on XTAL1 as it is not
internally resynchronized but immediately resets the microcontroller into its default reset
state. This asynchronous reset is required on power-up of the chip and may be used during
catastrophic situations. Note that rising edge of RSTIN pin is internally resynchronized
before exiting the reset condition. Therefore, only the entry of the this hardware reset is
asynchronous.
An asynchronous hardware reset is triggered when a low logic level on RSTIN and RPD/Vpp
pins is detected. To ensure a correct power-on reset, the RSTIN and RPD/Vpp pins must be
Figure 107 Internal reset circuitry
Asynchronous Reset
Internal
VCC
RSTIN
RPD/Vpp
Weak Pulldown
(~ 200 mA)
from/to Exit Powerdown
Circuit
VCC
flash device
trigger
Clock
Reset State
Machine
RSTOUT
SRST instruction
watchdog overflow
RPD/Vpp
Reset
Signal
Q
Clr
Set
EINIT instruction
Reset Sequence (512 CPU clock cycles)
Clr
BDRSTEN
