ST10R272L - SYNCHRONOUS SERIAL PORT
248/320
The chip enable lines are selected through the control bits SSPSEL0 and SSPSEL1. Note
that these automatic chip enable lines can be extended through normal IO pins, which,
however, must be activated and deactivated through software. To avoid conflicts with the
automatic chip enable lines, the combination ‘00’ for SSPSEL1..0 disables these lines, and
should be programmed when using IO lines as additional chip enable signals.
It is also possible to activate both chip enable lines with the combination ‘11’ for
SSPSEL1..0. This can be used if the same information has to be transferred to several
slaves simultaneously (message broadcast), providing that all slave peripherals use the
same clock configuration. Note that this option should only be used for write operation, since
for read operations, a conflict on the data line SSPDAT could occur if several slave
peripherals try to drive this line.
13.2.8 Using the SSP chip enable and clock lines for output functions
Note that the polarity and output control bits directly influence the lines SSPCLK, SSPCE0
and SSPCE1, regardless whether a transfer is in progress or not. It is recommended not to
reprogram these control bits while a transfer is in progress to avoid false operation of the
addressed slave peripheral(s).
However, if no transfer is in progress or the SSP is not used at all, the polarity and output
control bit can be used to perform general purpose output functions on the pins SSPCLK,
SSPCE0 and SSPCE1. The possible options are:
•
Output a low level.
•
Output a high level.
•
High-impedance (tri-state). The pin can be used as a general purpose I/O through Port 4
P4 register if this port line is configured as an input through DP4 register.
13.2.9 Continuous transfer modes
In order to simplify communication with some standard slave devices such as EEPROMs, a
continuous transfer mode is implemented in the SSP. This mode is distinguished from the
normal mode in that the chip enable line is not deactivated automatically after a transfer is
completed, but instead remains active until the mode is switched back from continuous
mode (SSPCM = ‘1’) to normal mode (SSPCM = ‘0’). Thus, consecutive transfers can be
performed while holding the chip enable line active during the entire procedure. This
condition keeps most peripheral slave devices in the operational mode initiated through the
first command transfer. EEPROMs, for instance, are placed into a read mode through first
transferring a read command to it. This command is followed by the start address of the
location to be read. After this, the EEPROM transfers the data stored in the specified
address to the master. If now the chip enable line is deactivated, the EEPROM cancels the
read mode and returns to idle mode. A new read operation must again start with the read
