ST10R272L - CENTRAL PROCESSING UNIT
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The on-chip peripheral units of the ST10R272L work almost independently of the CPU, with
a separate clock generator. Data and control information is interchanged between the CPU
and these peripherals via Special Function Registers (SFRs). Whenever peripherals need a
non-deterministic CPU action, an on-chip Interrupt Controller compares all pending
peripheral service requests against each other, and prioritizes one of them. If the priority of
the current CPU operation is lower than the priority of the selected peripheral request, an
interrupt will occur.
There are two types of interrupt processing:
•
Standard interrupt processing: forces the CPU to save the current program status and
the return address on the stack, before branching to the interrupt vector jump table.
•
PEC interrupt processing: steals one machine cycle from the current CPU activity to
perform a single data transfer via the on-chip Peripheral Event Controller (PEC).
System errors, detected during program execution (hardware traps) or an external
non-maskable interrupt, are processed as standard interrupts with high priority.
In contrast to other on-chip peripherals, there is a close conjunction between the Watchdog
Timer and the CPU. If enabled, the Watchdog Timer must be serviced by the CPU within a
programmable period of time, otherwise it will reset the chip. In this way, the Watchdog Timer
Figure 8 CPU block diagram
16
16
Internal
RAM
1KByte
R15
R0
General
Purpose
Registers
R0
R15
MDH
MDL
Barrel-Shift
Mul./Div.-HW
Bit-Mask Gen.
ALU
16-Bit
Context Ptr
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Code Seg. Ptr.
CPU
IDX0
IDX1
QX1
QX0
QR0
QR1
SP
STKOV
STKUN
Exec. Unit
Instr. Ptr
Instr. Reg
4-Stage
Pipeline
PSW
SYSCON
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
Data Pg. Ptrs
