ST10R272L - GENERAL PURPOSE TIMER UNITS
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timer can be a positive, a negative, or both a positive and a negative transition at this pin. Bit
field T6I in control register T6CON selects the triggering transition (see table below). The
maximum input frequency which is allowed in counter mode is
f
CPU
/8. To ensure that a
transition of the count input signal which is applied to T6IN is correctly recognized, its level
should be held high or low for at least 4 CPU clock cycles before it changes.
11.2.2 GPT2 Auxiliary Timer T5
The auxiliary timer T5 can be configured for timer, gated timer, or counter mode with the
same options for the timer frequencies and the count signal as the core timer T6. In addition
Figure 86 Block diagram of core timer T6 in counter mode
T6I
Triggering Edge for Counter Increment / Decrement
0 0 0
None. Counter T6 is disabled
0 0 1
Positive transition (rising edge) on T6IN
0 1 0
Negative transition (falling edge) on T6IN
0 1 1
Any transition (rising or falling edge) on T6IN
1 X X
Reserved. Do not use this combination
Table 39 GPT2 core timer T6 (counter mode) input edge selection
T6IN = P5.12
T6EUD = P5.10
T6OUT = P3.1
x = 6