ST10R272L - CENTRAL PROCESSING UNIT
41/320
.
4.1.4 Pipeline
effects
Additional hardware takes account of any causal dependencies on instructions in different
pipeline stages. This hardware (i.e. for ’forwarding’ operand read and write values) resolves
most of the conflicts (e.g. multiple usage of buses) and prevents the pipeline from becoming
noticeable to the user. However, there are some cases where the fact that the ST10R272L is
a pipelined machine, requires attention by the programmer. In these cases, the delays
caused by pipeline conflicts can be used by other instructions, to optimize performance.
These cases are outlined below:
Context Pointer Updating
An instruction which calculates a physical GPR operand address via the CP register, is not
usually capable of using a new CP value which is to be updated by an immediately
preceding instruction. Therefore, to make sure that the new CP value is used, at least one
instruction must be inserted between a CP-changing and a subsequent GPR-using
instruction, as shown in the following example:
Figure 11 Cache jump instruction pipelining
In:
SCXT CP, #0FC00h
;select a new context
In+1:
....
;must not be an instruction using a GPR
In+2:
MOV R0, #dataX
;write to GPR 0 in the new context
I
n+2
Cache Jmp
I
n
. . .
I
1
I
TARGET
Cache Jmp
I
n
I
2
I
1
I
TARGET
Cache Jmp
I
n+2
Cache Jmp
I
n
. . .
I
TARGET
(I
INJECT
)
Cache Jmp
I
n
I
1
I
TARGET
(I
INJECT
)
Cache Jmp
1 Machine
Cycle
FETCH
DECODE
EXECUTE
WRITEBACK
1st loop iteration
Injection
Injection of cached
Target Instruction
Repeated loop iteration
