ST10R272L - GENERAL PURPOSE TIMER UNITS
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Timer 3 in incremental interface mode
Incremental interface mode for the core timer T3 is selected by setting bit field T3M in
register T3CON to ‘110B’. In incremental interface mode the two inputs associated with
timer T3 (T3IN T3EUD) are used to interface to an incremental encoder. T3 is clocked by
Figure 72 Block diagram of core timer T3 in counter mode
T3I
Triggering Edge for Counter Increment / Decrement
0 0 0
None. Counter T3 is disabled
0 0 1
Positive transition (rising edge) on T3IN
0 1 0
Negative transition (falling edge) on T3IN
0 1 1
Any transition (rising or falling edge) on T3IN
1 X X
Reserved. Do not use this combination
Table 33 GPT1 core timer T3 (counter mode) input edge selection
T3IN = P3.6
T3EUD = P3.4
T3OUT = P3.3
x = 3
