ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC)
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5.2.7
Accumulator shifter
The Accumulator shifter is a parallel shifter with a 40-bit input and a 40-bit output. The
source operand of the shifter is the Accumulator and the possible shifting operations are:
•
No shift (Unmodified)
•
Up to 8-bit Arithmetic Left Shift
•
Up to 8-bit Arithmetic Right Shift
E, SV and SL bits from MSW are affected by Left shifts, therefore if the saturation
mechanism is enabled (MS), the behavior is similar to the one of the arithmetic unit. The
carry flag C is also affected by left shifts.
5.2.8
Repeat unit
The MAC includes a repeat unit allowing the repetition of some co-processor instructions up
to 2
13
(8192) times. The repeat count may be specified either by an immediate value (up to
31 times) or by the content of the Repeat Count (bits 12 to 0) in the MAC Repeat Word
(MRW). If the Repeat Count equals “N” the instruction will be executed “N+1” times. At each
iteration of a cumulative instruction the Repeat Count is tested for zero. If it is zero the
instruction is terminated else the Repeat Count is decremented and the instruction is
repeated. During such a repeat sequence, the Repeat Flag in MRW is set until the last
execution of the repeated instruction.
The syntax of repeated instructions is shown in the following examples:
In example 1, the instruction is repeated according to a 5-bit immediate value. The Repeat
Count in MRW is automatically loaded with this value minus one (MRW=23).
In this example, the instruction is repeated according to the Repeat Count in MRW. Notice
that due to the pipeline processing at least one instruction should be inserted between the
write of MRW and the next repeated instruction.
Repeat sequences may be interrupted. When an interrupt occurs during a repeat sequence,
the sequence is stopped and the interrupt routine is executed. The repeat sequence
resumes at the end of the interrupt routine. During the interrupt, MR remains set, indicating
that a repeated instruction has been interrupted and the Repeat Count holds the number
1
Repeat #24 times
CoMAC[IDX0+],[R0+]
; repeated 24 times
1
MOV MRW, #00FFh
; load MRW
NOP
; instruction latency
Repeat MRW times
CoMACM [IDX1-],[R2+]
; repeated 256 times
