ST10R272L - SYNCHRONOUS SERIAL PORT
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SYNCHRONOUS SERIAL PORT
The Synchronous Serial Port SSP provides high-speed serial communication with external
slave devices such as EEPROM, via a three-wire interface similar to the SPI protocol. The
interface lines are:
•
SSPCLK: Serial clock output. Driven by the ST10R272L (master) to the peripheral
(slave) which is selected for transfer.
•
SSPDAT: Bi-directional serial data line. Data is transferred between the ST10R272L and
the peripheral at up to 10 MBit/s.
•
SSPCE0,1: Serial peripheral chip enable signals 0 and 1. These signals select one of he
slaves connected to the SSP for transfer.
The SSP transmits 1...3 bytes or receives 1 byte after sending 1...3 bytes synchronously to
a shift clock which is generated by the SSP. The SSP can start shifting with the LSB or with
the MSB and allows to select shifting and latching clock edges as well as the clock polarity.
Up to two chip select lines may be activated in order to direct data transfers to one or both of
two peripheral devices.
One general interrupt vector is provided for the SSP.
Figure 97 Synchronous serial port SSP block diagram
VR02079B
Chip
Enable
Control
SSP Control
Block
Status
X BUS
Transmit Buffers
Registers SSPTBx
Receive Buffers
Registers SSPRB
Control
Pin
XP1INT
Clock Rate
Divider
Control
Clock
Clock
Shift
Clock
CPU
Receive/Transmit
Int. Request
SSPLCK
SSPCE0
SSPCE1
SSPDAT