ST10R272L - EXTERNAL BUS INTERFACE
172/320
9.4.4
Precautions and hints
•
The external bus interface is enabled as long as at least one of the BUSCON registers
has its BUSACT bit set.
•
PORT1 will output the intra-segment address as long as at least one of the BUSCON
registers selects a demultiplexed external bus, even for multiplexed bus cycles.
•
The address areas defined via registers ADDRSEL1 and ADDRSEL2 may not overlap
address areas defined via registers ADDRSEL3 and ADDRESEL4. The operation of the
EBC will be unpredictable in such a case.
•
The address areas defined via registers ADDRSELx may overlap internal address
areas. Internal accesses will be executed in this case.
•
For any access to an internal address area the EBC will remain inactive (see EBC Idle
State).
9.5
EBC idle state
When the external bus interface is enabled, but no external access is currently executed, the
EBC is idle. During this idle state the external interface appears in the following way:
•
PORT0 goes into high impedance (floating)
•
PORT1 (if used for the bus interface) drives the address used last
•
Port 4 (the activated pins) drives the segment address used last
•
Port 6 drives the CS signal corresponding to the address (see above), if enabled
•
ALE remains inactive (low)
•
RD/WR remain inactive (high)
9.6
External bus arbitration
In high performance systems it may be efficient to share external resources like memory
banks or peripheral devices among more than one controller. The ST10R272L supports this
approach with the possibility to arbitrate the access to its external bus, i.e. to the external
devices.
This bus arbitration allows an external master to request the ST10R272L’s bus via the HOLD
input. The ST10R272L acknowledges this request via the HLDA output and will float its bus
lines in this case. The CS outputs may provide internal pullup devices. The new master may
now access the peripheral devices or memory banks via the same interface lines as the
ST10R272L. During this time the ST10R272L can keep on executing, as long as it does not
need access to the external bus. All actions that just require internal resources like
instruction or data memory and on-chip peripherals, may be executed in parallel.
