ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC)
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5.2
MAC operation
5.2.1
Instruction pipelining
All MAC instructions use the 4-stage pipeline. During each stage the following tasks are
performed:
•
FETCH: All new instructions are double-word instructions.
•
DECODE: If required, operand addresses are calculated and the resulting operands are
fetched. IDX and GPR pointers are post-modified if necessary.
Figure 17 MAC architecture
Operand2
Operand1
Control Unit
Repeat Unit
ST10 Core
Interrupt
Controller
MSW
MRW
MAH
MAL
MCW
Flags MAE
Mux
Data
8-bit Left/Right
Shifter
Mux
Mux
Sign Extend
16 x 16
Concatenation
signed/unsigned
Multiplier
40-bit Signed Arithmetic Unit
0h
0h
08000h
40
16
40
40
32
32
16
40
40
40
40
40
40
Scaler
A
B
Limiter
