ST10R272L - EXTERNAL BUS INTERFACE
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In this case Port 4 outputs four, two or no address lines at all. It outputs all 8 address lines,
if an address space of 16 MBytes is used.
Note
When the on-chip SSP Module is to be used the segment address output on Port 4
must be limited to 4 bits (i.e. A19...A16) in order to enable the alternate function of
the SSP interface pins.
Bit SGTDIS of SYSCON register defines whether or not the CSP register is saved
during interrupt entry.
9.2.1
Multiplexed bus modes
In the multiplexed bus modes the 16-bit intra-segment address as well as the data use
PORT0. The address is time-multiplexed with the data and has to be latched externally. The
width of the required latch depends on the selected data bus width, i.e. an 8-bit data bus
requires a byte latch (the address bits A15...A8 on P0H do not change, while P0L
multiplexes address and data), a 16-bit data bus requires a word latch (the least significant
address line A0 is not relevant for word accesses).
The upper address lines (An...A16) are permanently output on Port 4 (if segmentation is
enabled) and do not require latches.
The EBC initiates an external access by generating the Address Latch Enable signal (ALE)
and then placing an address on the bus. The falling edge of ALE triggers an external latch to
capture the address. After a period of time during which the address must have been latched
externally, the address is removed from the bus. The EBC now activates the respective
command signal (RD, WR, WRL, WRH). Data is driven onto the bus either by the EBC (for
write cycles) or by the external memory/peripheral (for read cycles). After a period of time,
which is determined by the access time of the memory/peripheral, data become valid.
Read cycles: Input data is latched and the command signal is now deactivated. This causes
the accessed device to remove its data from the bus which is then tri-stated again.
