ST10R272L - PARALLEL PORTS
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Figure 39 Block diagram of port 4 pin P4.0 to P4.3
Figure 40 Block diagram of port 4 pins SSPCE1/ A20, SSPCE0 / A21, SSPCLK / A2
VR02075B
Output
Buffer
MUX
1
0
Alternate
Data
Output
Latch
Port Output
0
1
MUX
Write P4.y
Read P4.y
Enable
Function
Alternate
0
1
MUX
Read DP4.y
Write DP4.y
Direction
'1'
Input
Latch
Clock
Latch
s
u
B
l
a
n
r
e
t
n
I
P4.y
y = 3...0
VR02075C
Output
Buffer
MUX
1
0
Alternate
Data
Output
Latch
Port Output
0
1
MUX
Write P4.y
Read P4.y
Enable
Function
Alternate
0
1
MUX
Read DP4.y
Write DP4.y
Direction
'1'
Input
Latch
Clock
Latch
s
u
B
l
a
n
r
e
t
n
I
P4.y
y = 4, 5, 7
Signal
Control
SSP
0
1
MUX
Signal
SSP
SSP
Enabled
