ST10R272L - ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE
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TXD0/P3.10 and received on pin RXD0/P3.11. These signals are alternate functions of Port
3 pins.
8-bit data frames either consist of 8 data-bits D7...D0 (S0M=’001b’), or of 7 data-bits
D6...D0 plus an automatically generated parity bit (S0M=’011b’). Parity may be odd or even,
depending on bit S0ODD in register S0CON. An even parity bit will be set, if the
modulo-2-sum of the 7 data bits is ‘1’. An odd parity bit will be cleared in this case. Parity
checking is enabled via bit S0PEN (always OFF in 8-bit data mode). The parity error flag
S0PE will be set along with the error interrupt request flag, if a wrong parity bit is received.
The parity bit itself will be stored in bit S0RBUF.7.
9-bit data frames consist of either, 9 data-bits D8...D0 (S0M=’100b’), of 8 data-bits D7...D0
plus an automatically generated parity bit (S0M=’111b’), or of 8 data-bits D7...D0 plus
wake-up bit (S0M=’101b’). Parity may be odd or even, depending on bit S0ODD in register
S0CON. An even parity bit will be set, if the modulo-2-sum of the 8 data bits is ‘1’. An odd
parity bit will be cleared in this case. Parity checking is enabled via bit S0PEN (always OFF
in 9-bit data and wake-up mode). The parity error flag S0PE will be set along with the error
Figure 92 Asynchronous mode of serial channel ASC0
