ST10R272L - ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE
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interrupt request flag, if a wrong parity bit is received. The parity bit itself will be stored in bit
S0RBUF.8.
In wake-up mode, received frames are only transferred to the receive buffer register if the 9th
bit (the wake-up bit) is ‘1’. If this bit is ‘0’, no receive interrupt request will be activated and no
data will be transferred.
This feature may be used to control communication in multi-processor system:
When the master processor wants to transmit a block of data to one of several slaves, it first
sends out an address byte which identifies the target slave. An address byte differs from a
data byte in that the additional 9th bit is a '1' for an address byte and a '0' for a data byte, so
no slave will be interrupted by a data 'byte'. An address 'byte' will interrupt all slaves
(operating in 8-bit data + wake-up bit mode), so each slave can examine the 8 LSBs of the
received character (the address). The addressed slave will switch to 9-bit data mode (e.g. by
clearing bit S0M.0), which enables it to also receive the data bytes that will be coming
(having the wake-up bit cleared). The slaves that were not being addressed, remain in 8-bit
data + wake-up bit mode, ignoring the following data bytes.
Asynchronous transmission begins at the next overflow of the divide-by-16 counter (see
figure above), provided that S0R is set and data has been loaded into S0TBUF. The
transmitted data frame consists of three basic elements:
•
the start bit
Figure 93 Asynchronous 8-bit data frames
Figure 94 Asynchronous 9-bit data frames
2nd
Stop
Bit
Start
Bit
D0
(LSB)
D1
D2
D3
D4
D5
D6
D7 /
Parity
(1st)
Stop
Bit
2nd
Stop
Bit
Start
Bit
D0
(LSB)
D1
D2
D3
D4
D5
D6
9th
Bit
(1st)
Stop
Bit
D7
• Data Bit D8
• Parity
• Wake-up Bit
