ST10R272L - CENTRAL PROCESSING UNIT
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When a multiplication or division is interrupted before its completion, and when a new
multiply or divide operation is to be performed within the interrupt service routine, registers
MDL, MDH and MDC must be saved, to avoid erroneous results.
MDH (FE0Ch / 06h)
SFR
Reset Value: 0000h
MDL (FE0Eh/ 07h)
SFR
Reset Value: 0000h
The multiply/divide control register MDC
This bit addressable 16-bit register is implicitly used by the CPU for multiplication or division.
It is used to store the control information for the multiply or divide operation. The MDC
register is updated by hardware during each single cycle of a multiply or divide instruction.
When a division or multiplication is interrupted before completion, and the multiply/divide unit
is required, the MDC register must first be saved with registers MDH and MDL (to be able to
restart the interrupted operation later), and then it must be cleared to be prepared for the
new calculation. After completion of the new division or multiplication, the state of the
interrupted multiply or divide operation must be restored.
Note
The MDRIU flag is the only portion of the MDC register which can be
modified. The other parts of the MDC register are reserved for hardware use
Bit
Function
mdh
Specifies the high order 16 bits of the 32-bit multiply and divide register MD.
Bit
Function
mdl
Specifies the low order 16 bits of the 32-bit multiply and divide register MD.
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
rw
mdh
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
rw
mdl