ST10R272L - ARCHITECTURAL OVERVIEW
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of a hardware trap is, additionally, signified by an individual bit in the trap flag register (TFR).
Except when another higher-priority trap service is in progress, a hardware-trap will interrupt
any actual program execution. In turn, hardware-trap services can not, normally be
interrupted by a standard-interrupt or PEC-interrupt.
2.2
On-chip system resources
The ST10R272L provides a number of powerful system resources designed around the
CPU.
2.2.1
Peripheral event controller (PEC) and interrupt control
The Peripheral Event Controller responds to an interrupt request with a single data-transfer
(word or byte) which consumes one instruction cycle, and does not require a ‘save and
restore machine-status’. Each interrupt source is prioritized in every machine cycle, in the
interrupt control block. If a PEC service is selected, a PEC transfer is started. If a
CPU-interrupt service is requested, the current CPU priority level (stored in the PSW
register) is tested to determine whether a higher-priority interrupt is currently being serviced.
When an interrupt is acknowledged, the current machine-state is saved on the internal
system-stack, and the CPU branches to the system specific vector for the peripheral.
The PEC contains a set of SFRs which store the count value and control bits for eight data
transfer channels. In addition, the PEC uses a dedicated area of RAM which contains the
source and destination addresses. The PEC is controlled by SFRs containing the channel
configuration.
An individual PEC-transfer counter is implicitly decremented for each PEC service, except
when performing in the continuous-transfer mode. When the counter reaches zero, a
standard-interrupt is performed to the vector location related to the corresponding source.
PEC services are very well suited, for example, to move register contents to or from a
memory table. The ST10R272L has 8 PEC channels, each of which offers fast
interrupt-driven data transfer capabilities.
2.2.2 Memory
areas
The memory space of the ST10R272L is configured in a Von Neumann architecture which
means that code memory, data memory, registers and IO ports are organized within the
same linear address spaces. The entire memory space can be accessed bytewise or
wordwise. Particular portions of the on-chip memory are directly bit addressable.
A 1KByte 16-bit wide internal RAM is used for variables, register banks, and the system
stack. It also contains the PEC pointers and the bit-addressable space.
The CPU has an actual register context, consisting of up to 16 wordwide and/or bytewide
GPRs, which are physically located within the on-chip RAM area. A Context Pointer (CP)
register determines the base address of the active register bank accessed by the CPU. The
