ST10R272L - SYNCHRONOUS SERIAL PORT
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13.1
XBUS implementation
The SSP is implemented as an XPERipheral onto the XBUS in the address range 00EF00h
- 00EFFFh, a 256 Byte range (10 byte addresses used). It is connected via a 16-bit
demultiplexed bus, without waitstates, allowing word and byte accesses via the CPU or the
PEC.
From a user’s point of view, the XBUS can be regarded as an internal representation of the
external bus in the 16-bit demultiplexed mode, allowing the fastest possible word and byte
accesses by the CPU or the PEC, to the SSP registers. The SSP registers are in a special
SSP address area of 256 bytes which is mapped into segment 0 and uses addresses EF00h
through EFFFh (10 bytes addresses used).
13.2
SSP registers
Bit 2 of control register SYSCON serves as an enable/disable control for the SSP module.
This bit is named XSSPEN (Xperipheral SSP ENable Control). After reset, XSSPEN is set to
‘0’, and the SSP is disabled.
The four upper pins of Port4 can be used for segment address lines or general purpose I/Os,
(refer to “Port 4” on page 129). In order to use the SSP, bit XSSPEN must first be set to 1.
Note that SYSCON register can only be written to during the initialization phase after a reset
until the EINIT instruction is executed. After the EINIT instruction, the SYSCON register is
locked against modifications until the next reset.
When the SSP is enabled, the four upper pins of Port4 can not be used as general purpose
I/O. Note that the segment address selection done via the system start-up configuration
during reset has priority and overrides the SSP functions on these pins.
The SSP registers are organized as five 16-bit registers located on word addresses.
However, all registers may be accessed bytewise in order to select special actions without
