ST10R272L - GENERAL PURPOSE TIMER UNITS
221/320
The count directions of the two concatenated timers are not required to be the same. This
offers a wide variety of different configurations.
T6 can operate in timer, gated timer or counter mode in this case.
GPT2 capture/reload register CAPREL in capture mode
This 16-bit register can be used as a capture register for the auxiliary timer T5. This mode is
selected by setting bit T5SC=‘1’ in control register T5CON. Bit CT3 selects the external input
pin CAPIN or the input pins of timer T3 as the source for a capture trigger. Either a positive,
a negative, or both a positive and a negative transition at this pin can be selected to trigger
the capture function or transitions on input T3IN or input T3EUD or both inputs T3IN and
T3EUD. The active edge is controlled by bit field CI in register T5CON.
The maximum input frequency for the capture trigger signal at CAPIN is
f
CPU
/4. To ensure
that a transition of the capture trigger signal is correctly recognized, its level should be held
for at least 4 CPU clock
cycles before it changes.
When the timer T3 capture trigger is enabled (CT3=’1’) the CAPREL register captures the
contents of T5 upon transitions of the selected input(s). These values can be used to
measure T3’s input signals. This is useful e.g. when T3 operates in incremental interface
mode, in order to derive dynamic information (speed, acceleration, deceleration) from the
input signals.
Figure 88 Concatenation of core timer T6 and auxiliary timer T5
*)
Note: Line only affected by over/underflows of T6, but NOT by software modifications of T6OTL.
T6OUT = P3.1
x =5 y = 6
