ST ST10R272L, User Manual

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ST10R272L - INTERRUPT AND TRAP FUNCTIONS
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6.9.3 Trap flag register
The bit-addressable Trap Flag Register (TFR) allows a trap service routine to identify the
kind of trap which caused the exception. Each trap function is indicated by a separate
request flag. When a Hardware Trap occurs, the corresponding request flag in register TFR
is set to ’1’.
Hardware Reset RESET 00’0000
h
00
h
III
Software Reset RESET 00’0000
h
00
h
III
Watchdog Timer Overflow RESET 00’0000
h
00
h
III
class-A Hardware Traps:
Non-Maskable Interrupt NMI NMITRAP 00’0008
h
02
h
II
Stack Overflow STKOF STOTRAP 00’0010
h
04
h
II
Stack Underflow STKUF STUTRAP 00’0018
h
06
h
II
class-B Hardware Traps:
Undefined opcode UNDOPC BTRAP 00’0028h 0A
h
I
Protected instruction fault PRTFLT BTRAP 00’0028h 0A
h
I
Illegal word operand access ILLOPA BTRAP 00’0028h 0A
h
I
Illegal instruction access ILLINA BTRAP 00’0028h 0A
h
I
Illegal external bus access ILLBUS BTRAP 00’0028h 0A
h
I
MAC trap MACTRP BTRAP 00’0028h 0A
h
I
Reserved [2C
h
– 3C
h
] [0B
h
– 0F
h
]
Software Traps
TRAP Instruction Any [00’0000
h
– 00’01FC
h
]
steps of 4
h
Any
[00
h
– 7F
h
]
Current
CPU
Priority
Exception Condition Trap Flag Trap Vector
Vector
Location Trap
Number Trap
Priority
Table 20 Exceptions or error conditions