ST10R272L - CENTRAL PROCESSING UNIT
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page base-address, together with the 14-bit page-offset, forms the physical 24/20/18-bit
address.
For Non-segmented Memory Mode, only the two least significant bits of the implicitly
selected DPP register are used to generate the physical address. Extreme care should be
taken when changing the content of a DPP register if a non-segmented memory
model is selected, otherwise unexpected results can occur.
In Segmented Memory Mode the selected number of segment address bits (9...2, 5...2 or
3...2) of the respective DPP register is output on the segment address pins (A23/A19/
A17...A16) of Port 4, for all external data accesses.
A DPP register can be updated by any instruction which is capable of modifying an SFR.
Due to the Internal Instruction Pipeline, a new DPP value can not be used for the operand
address calculation of an instruction immediately following the instruction which updates the
DPP register.
The context pointer CP
This non bit-addressable register is used to select the current register context. This means
that the CP register value determines the address of the first General Purpose Register
(GPR) in the current register bank (of up to 16 wordwide and/or bytewide GPRs).
Figure 13 Addressing via the data page pointers
1023
Data Pages
16-bit Data Address
0
15 14
14-bit
Intra-Page Address
(concatenated with
content of DPPx)
1022
1021
2
1
0
3
DPP3
DPP2
DPP1
DPP0
1 1
1 0
0 1
0 0
DPP Registers
After reset or with segmentation disabled the DPP registers select data pages 3...0.
All of the internal memory is accessible in these cases.