ST10R272L - SYSTEM PROGRAMMING
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18.9
Trap/interrupt entry and exit
Interrupt routines are entered when a requesting interrupt has a priority higher than the
current CPU priority level. Traps are entered regardless of the current CPU priority. When
either a trap or interrupt routine is entered, the machine state is preserved on the system
stack, and a branch to the appropriate trap/interrupt vector is made.
All trap and interrupt routines use the RETI (return from interrupt) instruction to exit from the
routine. This instruction restores the system state from the system stack and then branches
back to the location where the trap or interrupt occurred.
18.10
Inseparable instruction sequences
Some instructions, such as semaphore handling, require uninterruptable code sequences.
This is achieved by inhibiting interrupts during the respective code sequence - by disabling
and enabling them before and after the sequence. The ATOMIC instruction locks 1...4
instructions to an inseparable code sequence during which the interrupt system and Class
A Traps are disabled. A Class B Trap (illegal opcode, illegal bus access, etc.), however, will
interrupt the ATOMIC sequence since it indicates a severe hardware problem. The interrupt
inhibit caused by an ATOMIC instruction becomes active immediately, i.e. no other
instruction will enter the pipeline except the one that follows the ATOMIC instruction, and no
interrupt request will be serviced in between. In this way, all instructions requiring multiple
cycles or hold states are regarded as one instruction (e.g. MUL is one instruction). Any
instruction type can be used in an inseparable code sequence. For example:
ATOMIC #3
The following 3 instructions are locked (No NOP required)
18.11
Overriding the DPP addressing mechanism
The standard mechanism to access data locations uses one of the four data page pointers
(DPPx) which selects a 16 KByte data page, and a 14-bit offset within this data page. The
four DPPs allow immediate access to up to 64KByte of data. In applications with big data
arrays, especially in HLL applications using large memory models, this may require frequent
reloading of the DPPs, even for single accesses.
MOV
R0, #1234h
;Instruction 1 (no other instr. enters the
pipeline!)
MOV
R1, #5678h
;Instruction 2
MUL
R0, R1
;Instruction 3: MUL regarded as one instruction
MOV
R2, MDL
;This instruction is out of the scope of ATOMIC
;instruction sequence
