ST10R272L - WATCHDOG TIMER
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14.1
Watchdog timer operation
The current count value of the watchdog timer is contained in the watchdog timer register
WDT, which is a non-bitaddressable read-only register. The operation of the watchdog timer
is controlled by its bitaddressable watchdog timer control register WDTCON. This register
specifies the reload value for the high byte of the timer, selects the input clock prescaling
factor and provides a flag that indicates a watchdog timer overflow.
After any software reset, external hardware reset (see note), or watchdog timer reset, the
watchdog timer is enabled and starts counting up from 0000h with the frequency f
CPU
/2.
The input frequency may be switched to f
CPU
/128 by setting bit WDTIN. The watchdog timer
can be disabled via the instruction DISWDT (Disable Watchdog Timer). Instruction DISWDT
is a protected 32-bit instruction which will ONLY be executed during the time between a reset
and execution of either the EINIT (End of Initialization) or the SRVWDT (Service Watchdog
Timer) instruction. Either one of these instructions disables the execution of DISWDT.
When the watchdog timer is not disabled via instruction DISWDT, it will continue counting up,
even during idle mode. If it is not serviced by the instruction SRVWDT by the time the count
reaches FFFFh the watchdog timer will overflow and cause an internal reset. This reset will
pull the external reset indication pin RSTOUT low. It differs from a software or external
hardware reset in that bit WDTR (watchdog timer reset indication flag) of register WDTCON
will be set. A hardware reset or the SRVWDT instruction will clear this bit. Bit WDTR can be
examined by software in order to determine the cause of the reset.
A watchdog reset will also complete a running external bus cycle before starting the internal
reset sequence if this bus cycle does not use READY or samples READY active (low) after
the programmed waitstates. Otherwise the external bus cycle will be aborted.
After a hardware reset that activates the Bootstrap Loader the Watchdog Timer will be
disabled
To prevent the watchdog timer from overflowing, it must be serviced periodically by the user
software. The watchdog timer is serviced with the instruction SRVWDT, which is a protected
32-bit instruction. Servicing the watchdog timer clears the low byte and reloads the high byte
of the watchdog time register WDT with the preset value in bit field WDTREL, which is the
high byte of register WDTCON. Servicing the watchdog timer will also reset bit WDTR. After
being serviced the watchdog timer continues counting up from the value (<WDTREL> * 2
8
).
Instruction SRVWDT has been encoded in such a way that the chance of unintentionally
servicing the watchdog timer (eg. by fetching and executing a bit pattern from a wrong
location) is minimized. When instruction SRVWDT does not match the format for protected
instructions, the Protection Fault Trap will be entered, rather than the instruction be
executed.
