ST10R272L - PWM MODULE
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with the contents of the associated counter PT3. When a match is found between the
counter and PP3 register, the counter is either reset to 0000h, or the count direction is
switched from counting up to counting down, depending on the selected operating mode of
that PWM channel.
PP3 (F03Eh / 1Fh)
ESFR
Reset Value: 0000h
10.2.3 Pulse width register PW3
This 16-bit register holds the actual PWM pulse width value, which corresponds to the duty
cycle of the PWM signal. This register is connected to a 16-bit shadow register. The CPU
accesses the PW3 register while the hardware compares the contents of the shadow
register with the content of the counter PT3. The shadow register is loaded from the PW3
register at the beginning of every new PWM cycle, or upon a write access to PW3, while the
timer is stopped.
When the counter value is greater than or equal to the shadow register value, the PWM
signal is set, otherwise it is reset. The output of the comparator may be described by the
Boolean formula:
PWM
output signal
= ([PT3]
>
[PW3 shadow register]
PW3 (F036h / 1Bh)
SFR
Reset Value: 0000h
10.2.4 PWM control register PWMCON0
This 16-bit control register controls the function of the timers of the PWM channel, and holds
the individual interrupt enable and request flags.
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
rw
PP3
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
rw
PW3
