ST ST10R272L, User Manual

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ST10R272L - INTERRUPT AND TRAP FUNCTIONS
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6.1.2 Normal interrupt processing and PEC service
During each instruction cycle, one of the sources which require PEC or interrupt processing
is selected according to its interrupt priority. Interrupts and PEC request priority is
programed in two levels.
•
CPU interrupt priority level - defines the priority level for the arbitration of requests.
•
Group priority - defines the internal order for simultaneous requests of the same priority.
At the end of each instruction cycle, the interrupt system decides which source request has
the highest priority. This source request is then serviced if its priority is higher than the
current CPU priority in the PSW register.
External Interrupt 3 CC11IR CC11IE CC11INT 6Ch 1Bh
GPT1 Timer 2 T2IR T2IE T2INT 88h 22h
GPT1 Timer 3 T3IR T3IE T3INT 8Ch 23h
GPT1 Timer 4 T4IR T4IE T4INT 90h 24h
GPT2 Timer 5 T5IR T5IE T5INT 94h 25h
GPT2 Timer 6 T6IR T6IE T6INT 98h 26h
GPT2 CAPREL Register CRIR CRIE CRINT 9Ch 27h
ASC0 Transmit S0TIR S0TIE S0TINT A8h 2Ah
ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 11Ch 47h
ASC0 Receive S0RIR S0RIE S0RINT ACh 2Bh
ASC0 Error S0EIR S0EIE S0EINT B0h 2Ch
PWM Channel 3 PWMIR PWMIE PWMINT FCh 3Fh
SSP Interrupt XP1IR XP1IE XP1INT 104h 41h
PLL Unlock XP3IR XP3IE XP3INT 10Ch 43h
Source of Interrupt or PEC
Service Request Request
Flag Enable
Flag Interrupt
Vector Vector
Location Trap
Number
Table 13 List of possible interrupt sources, flags, vector and trap numbers