ST10R272L - PARALLEL PORTS
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PARALLEL PORTS
The ST10R272L provides up to 77 parallel I/O lines organized into six 8-bit I/O ports (POH,
POL, P1H, P1L, P4, P6), two 4-bit I/O ports (P2, P7), one 15 bit I/O port (P3) and one 6-bit
input port (P5). The port lines can be used for general purpose input/output, controlled by
software, or may be used implicitly by the integrated peripherals or the external bus
controller.
For low power devices:
•
Port 5 pins are 5 V tolerant and fail-safe (voltage max. with respect to Vss is -0.5 to 5.5,
even if the chip is non powered)
•
XTAL1 and XTAL2 are 3 V tolerant (voltage max. respect to Vss is -0.5 to V
DD
+ 0.5)
•
All other pins are 5 V tolerant (voltage max. respect to Vss is -0.5 to 5.5 only if chip is
powered)
For more information on this, refer to the ST10R272L Data Sheet.
Using the port as a general purpose I/O line
All port lines are bit addressable, and all input/output lines are individually (bit-wise)
programmable as inputs or outputs via direction registers (except Port 5). The I/O ports are
true bidirectional ports which are switched to high impedance state when configured as
inputs. The output drivers of three I/O ports (2, 3, 6) can be configured (pin by pin) for push/
pull operation or open-drain operation via control registers. The logic level of a pin is clocked
into the input latch once per CPU clock cycle, regardless whether the port is configured for
input or output.
A write operation to a port pin configured as an input causes the value to be written into the
port output latch, while a read operation returns the latched state of the pin itself. A
read-modify-write operation reads the value of the pin, modifies it, and writes it back to the
output latch.
Writing to a pin configured as an output (DPx.y=‘1’) causes the output latch and the pin to
have the written value, since the output buffer is enabled. Reading this pin returns the value
