ST10R272L - EXTERNAL BUS INTERFACE
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The read/write delay is controlled via the RWDCx bits in the BUSCON registers. The
command(s) will be delayed, if bit RWDCx is ‘0’ (default after reset).
9.3.5 READY/READY controlled bus cycles
The active level of the ready pin can be set to READY or READY by the RDYPOL bit 13 in the
BUSCON register.
Where the programmable waitstates are not enough, or where the response (access) time of
a peripheral is not constant, the ST10R272L provides external bus cycles that are
terminated by a READY or READY input signal (synchronous or asynchronous). In this case
the ST10R272L first inserts a programmable number of waitstates (0...7) and then monitors
the READY or READY line to determine the actual end of the current bus cycle. The external
device drives READY or READY low in order to indicate that data has been latched (write
cycle) or are available (read cycle).
Figure 59 Read/write delay
