ST10R272L - PWM MODULE
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operation of channel 3 is controlled by the PWMCON0 and PWMCON1registers, and the
interrupt control and status is handled by the PWMIC interrupt control register.
Note
For the following descriptions the comparison of the timer contents and the PWM
value is performed through a ’greater than or equal to’ comparison: PWM Output
Signal = [PT3] > [PW3]
10.1
Operating Modes
The PWM module provides three different operating modes:
•
Mode 0 - standard PWM generation (edge aligned PWM),
•
Mode 1 - symmetrical PWM generation (center aligned PWM),
•
Single shot mode.
Figure 64 PWM channel block diagram
PPx Period Register
Comparator
PTx
16-Bit Up/Down
Counter
Comparator
Shadow Register
PWx Pulse Width Reg.
Up/Down
Clear
Control
Output
Control
Write
Control
User Read &
Writable
MUX
: 64
f
CPU
XO
R
Latch P7.x
P7.x
