ST10R272L - CENTRAL PROCESSING UNIT
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available for instructions. For implicit stack operations (CALL or RET) the CSP register and
the IP are saved to and restored from the stack. After reset, the segmented memory mode is
selected.
Note
Bit SGTDIS controls whether the CSP register is pushed onto the system stack (in
addition to the IP and PSW registers) before an interrupt service routine is entered,
and whether it is re-popped when the interrupt service routine is left again.
System stack size (STKSZ)
This bitfield defines the size of the physical system stack located in the internal RAM. An
area of 32...512 words, or all of the internal RAM, may be dedicated to the system stack. A
‘circular stack’ mechanism makes it possible to use a bigger virtual stack than this dedicated
RAM area.
These techniques as well as the encoding of bitfield STKSZ are described in more detail in
“SYSTEM PROGRAMMING” on page 303.
Processor status word PSW
This bit-addressable register reflects the current state of the microcontroller. Two groups of
bits represent the current ALU status and the current CPU interrupt status. A separate bit
(USR0) in the PSW register provides a general-purpose user flag.
PSW (FF10h / 88h)
SFR
Reset Value: 0000h
Bit
Function
N
Negative Result
Set, when the result of an ALU operation is negative.
C
Carry Flag
Set, when the result of an ALU operation produces a carry bit.
V
Overflow Result
Set, when the result of an ALU operation produces an overflow.
Z
Zero Flag
Set, when the result of an ALU operation is zero.
HLD
EN
MUL
IP
USR0
-
N
Z
C
V
E
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
rw
rw
rw
rw
-
rw
rw
rw
-
rw
-
rw
IEN
-
-
ILVL
rw
