ST10R272L - MEMORY ORGANIZATION
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MEMORY ORGANIZATION
The memory space of theST10R272L is configured in a “Von Neumann” architecture. This
means that code and data are accessed within the same linear address space. All of the
physically separated memory areas, including internal RAM, the internal Special Function
Register Areas (SFRs and ESFRs), the address areas for integrated XBUS peripherals and
external memory are mapped into one common address space.
The ST10R272L provides a total addressable memory space of 16MBytes. This address
space is arranged as 256 segments of 64KBytes each, and each segment is subdivided into
four data pages of 16 KBytes each (see figure below).
Figure 4 Memory areas and address
XSSP
Data Page 0
Data Page 1
Data Page 2
Data Page 3
00’4000h
00’8000h
00’FFFFh
00’0000h
00’1FFFh
00’EF00h
00’EFFFh
Internal
memory
area
RAM/SFR
System Segment 0
64 K-Byte
External
memory
area
segment 255
segment 254
segment 2
segment 1
segment 0
FF’FFFFh
Data Page 1023
FF’0000h
FE’0000h
03’0000h
02’0000h
01’0000h
Data Page 3
Data Page 0
Address space
16 MByte
