ST10R272L - INTERRUPT AND TRAP FUNCTIONS
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INTERRUPT AND TRAP FUNCTIONS
The ST10R272L architecture supports several mechanisms for fast and flexible response to
the service requests that can be generated from various sources, internal or external to the
microcontroller. Any of these interrupt requests can be programmed to be serviced, either by
the Interrupt Controller or by the Peripheral Event Controller (PEC).
Normal Interrupt Processing: In a standard interrupt service, program execution is
suspended and a branch to the interrupt service routine is performed. The current program
status (IP, PSW, in segmentation mode also CSP) is saved on the internal system stack. A
prioritization scheme with 16 priority levels allows the user to specify the order in which
multiple interrupt requests are to be handled.
Interrupt Processing via the Peripheral Event Controller (PEC): For a PEC service, just
one cycle is ‘stolen’ from the current CPU activity. A PEC service is a single, byte or word
data transfer between any two memory locations, with an additional increment of either the
PEC source or the destination pointer. A PEC-transfer counter is decremented for each PEC
service, except in the continuous transfer mode. When this counter reaches zero, a standard
interrupt is performed to the corresponding source-related vector location. PEC services are
very well suited, for example, to the transmission or reception of blocks of data. The
ST10R272L has 8 PEC channels, each of which offers fast interrupt-driven data transfer
capabilities.
Trap Functions: Software interrupts are supported by means of the ‘TRAP’ instruction in
combination with an individual trap (interrupt) number. Trap functions are activated in
response to special conditions that occur during the execution of instructions. A trap can
also be caused externally by the Non-Maskable Interrupt pin NMI. Several Hardware Trap
functions are provided for handling erroneous conditions and exceptions that arise during
the execution of an instruction. Hardware Traps always have highest priority and cause
immediate system reaction. The software trap function is invoked by the TRAP instruction,
which generates a software interrupt for a specified interrupt vector. For all types of traps the
current program status is saved on the system stack.
External Interrupt Processing: Fast external interrupt inputs service external interrupts
with high precision requirements. These fast interrupt inputs include programmable edge
detection (rising edge, falling edge or both edges).
6.1
Interrupt system structure
The ST10R272L provides 20 separate interrupt nodes that may be assigned to 16 priority
levels. In order to support modular and consistent software design techniques, each source
of an interrupt or PEC request is supplied with a separate interrupt control register and
interrupt vector.
A control register contains an interrupt request flag, an interrupt enable flag and an interrupt
priority bitfield for each of the possible interrupt sources. Via its related register, each source