ST10R272L - EXTERNAL BUS INTERFACE
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When the ST10R272L needs access to its external bus while it is occupied by another bus
master, it demands it via the BREQ output.
The external bus arbitration is enabled by setting bit HLDEN in register PSW to ‘1’. This bit
may be cleared during the execution of program sequences, where the external resources
are required but cannot be shared with other bus masters. In this case the ST10R272L will
not answer to HOLD requests from other external masters.
The pins HOLD, HLDA and BREQ keep their alternate function (bus arbitration) even after
the arbitration mechanism has been switched off by clearing HLDEN.
All three pins are used for bus arbitration after bit HLDEN was set once.
9.6.1
Entering the hold state
Access to the ST10R272L’s external bus is requested by driving its HOLD input low. After
synchronizing this signal the ST10R272L will complete a current external bus cycle (if any is
active), release the external bus and grant access to it by driving the HLDA output low.
During hold state the ST10R272L treats the external bus interface as follows:
•
• Address and data bus(es) float to tri-state
•
• ALE is pulled low by an internal pulldown device
•
Command lines are pulled high by internal pullup devices (RD, WR/WRL, BHE/WRH)
•
CSx outputs are pulled high (push/pull mode) or float to tri-state (open drain mode)
