ST10R272L - CENTRAL PROCESSING UNIT
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Note
Ensure that the physical GPR address specified by the CP register and short
GPR address is always at an internal RAM location. Otherwise, unexpected
results may occur.
•
Do not set CP below 00’F600h or above 00’FDFEh.
•
Be careful using the upper GPRs with CP above 00’FDE0h.
The CP register can be updated by any instruction which is capable of modifying an SFR.
Due to the internal instruction pipeline, a new CP value can not be used for GPR address
calculation of the instruction immediately following the instruction updating the CP register.
The switch context instruction (SCXT) saves the content of the CPregister on the stack and
updates it with a new value in one machine cycle.
CP (FE10h / 08h)
SFR
Reset Value: FC00h
Bit
Function
cp
Modifiable portion of register CP
Specifies the (word) base address of the current register bank.
When writing a value to register CP with bits CP.11...CP.9 = ‘000’, bits CP.11...CP.10
are set to ‘11’ by hardware, in all other cases all bits of bit field “cp” receive the written
value.
1
0
1
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
r
rw
r
r
r
1
1
r
cp
