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ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC)

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MULTIPLY-ACCUMULATE UNIT (MAC)

The MAC is a specialized co-processor added to the ST10R272L CPU core to improve the
performance of signal processing algorithms. It includes:

•

a multiply-accumulate unit

•

an address generation unit, able to feed the MAC unit with 2 operands per cycle

•

a repeat unit, to execute a series of multiply-accumulate instructions

New addressing capabilities enable the CPU to supply the MAC with up to 2 operands per
instruction cycle. MAC instructions: multiply, multiply-accumulate, 32-bit signed arithmetic
operations and the CoMOV transfer instruction have been added to the standard instruction
set. Full details are provided in the ‘ST10 Family Programming Manual’.

Figure 16 MAC architecture

MAC CoProcessor

dual-port

internal RAM

external
memory

memory

program

new addressing features

IDX0

IDX1

QX0

QX1

QR0

QR1

operands

control

program code

data buses

16 x16

multiplier

40-bit ALU

shifter

MCW MAL

MRW MAH

MSW

repeat unit

40-bit accumulator

Peripheral

interface

ST10R272L CPU

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Summary of Contents for ST10R272L

Page 1: ...ST10R272L USER S MANUAL Release 1 0...

Page 2: ...and interrupt control 15 2 2 2 Memory areas 15 2 2 3 External bus interface 16 2 3 SYSTEM CLOCK GENERATOR 17 2 3 1 PLL operation 19 2 3 2 Prescaler operation 19 2 3 3 Direct drive 19 2 3 4 Oscillator...

Page 3: ...stem configuration register SYSCON 47 5 MULTIPLY ACCUMULATE UNIT MAC 67 5 1 MAC FEATURES 68 5 2 MAC OPERATION 69 5 2 1 Instruction pipelining 69 5 2 2 Address generation 70 5 2 3 16 x 16 signed unsign...

Page 4: ...PONSE TIMES 98 6 7 PEC RESPONSE TIMES 100 6 8 EXTERNAL INTERRUPTS 102 6 8 1 Fast external interrupts 103 6 9 TRAPS 105 6 9 1 Software traps 105 6 9 2 Hardware traps 105 6 9 3 Trap flag register 106 6...

Page 5: ...S MODES 146 9 2 1 Multiplexed bus modes 147 9 2 2 Demultiplexed bus modes 148 9 2 3 Switching between bus modes 149 9 2 4 External data bus width 151 9 2 5 Disable enable control for pin BHE BYTDIS 15...

Page 6: ...3Single shot mode 182 10 2 PWM MODULE REGISTERS 185 10 2 1Up down counter PT3 185 10 2 2Period register PP3 185 10 2 3Pulse width register PW3 186 10 2 4PWM control register PWMCON0 186 10 2 5PWM con...

Page 7: ...gister 1 SSPCON1 242 13 2 3SSP transmit buffer registers SSPTBx 243 13 2 4Initialization 244 13 2 5Starting a transfer 244 13 2 6Performing a Write Operation 245 13 2 7Chip enable lines 247 13 2 8Usin...

Page 8: ...RESET 270 15 10APPLICATION SPECIFIC INITIALIZATION ROUTINE 271 15 10 1System start up configuration 272 15 10 2Emulation mode 273 15 10 3Adapt mode 274 15 10 4System clock configuration 274 15 10 5Ex...

Page 9: ...nal system stack 304 18 3 2Circular virtual Stack 305 18 3 3Linear stack 308 18 3 4User stacks 308 18 4 REGISTER BANKING 308 18 5 CALL PROCEDURE ENTRY AND EXIT 309 18 5 1Passing parameters on the syst...

Page 10: ...ew gives a general description of the ST10R272L device It describes in brief the CPU performance the on chip system resources the clock generator the peripheral blocks and the protected bits The detai...

Page 11: ...10R272L block diagram ST10 CORE 1KByte DPRAM Interrupt Controller Port 4 Port 1 8 bit 2x8 bit Port 0 2x8 bit Port 2 4 bit Port 6 8 bit I O CS 4 0 I O HOLD HLDA BREQ A 15 0 I O D 7 0 D 15 8 D 7 0 A 15...

Page 12: ...ores temporary data The system stack is allocated in the on chip RAM area and is accessed by the CPU via the stack pointer SP register Two separate SFRs STKOV and STKUN are compared against the stack...

Page 13: ...l registers from the decode stage PLAs Pipeline holds are primarily caused by wait states for external memory accesses and cause a signal to be held in the control registers Multiple cycle instruction...

Page 14: ...4 High performance branch call and loop processing Branch instructions only require one extra machine cycle when a branch is taken because the target address is pre calculated while decoding the inst...

Page 15: ...such as GPR or data4 for immediate shift value New MAC instruction addressing modes supply the MAC with up to 2 new operands per instruction cycle These allow indirect addressing with address pointer...

Page 16: ...which store the count value and control bits for eight data transfer channels In addition the PEC uses a dedicated area of RAM which contains the source and destination addresses The PEC is controlled...

Page 17: ...rformed by the External Bus Controller EBC It can be programmed either to Single Chip Mode when no external memory is required or to one of four different external memory access modes 16 18 20 24 bit...

Page 18: ...en by an external oscillator The oscillator can directly feed the external clock signal to the controller hardware through buffers and divides the external clock frequency by 2 or feeds an on chip pha...

Page 19: ...0H 7 5 CPU frequency fCPU fXTAL F Notes 1 1 1 FXTAL 4 Default configuration 1 1 0 FXTAL 3 1 0 1 FXTAL 2 1 0 0 FXTAL 5 0 1 1 FXTAL 1 Direct drive1 0 1 0 FXTAL 1 5 0 0 1 FXTAL 2 CPU clock via 2 1 presca...

Page 20: ...an interrupt request on PLL Unlock XP3INT interrupt node This occurs when the input clock is unstable and especially when the input clock fails completely e g due to a broken crystal In this case the...

Page 21: ...On chip peripheral blocks The ST10 family separates its peripherals from the core allowing peripherals to be added or removed without modifications to the core Each functional block processes data ind...

Page 22: ...odified by the peripheral the software write operation has priority Further details on peripheral timing are included in the specific sections about each peripheral 2 4 3 Programming hints All SFRs ar...

Page 23: ...where segmentation is enabled to access more than 64 KBytes of memory Port 6 provides optional bus arbitration signals BREQ HLDA HOLD and chip select signals Port 3 includes alternate functions of ti...

Page 24: ...due to hardware or software related failures the software fails to maintain the watchdog timer it will overflow generating an internal hardware reset and pulling the RSTOUT pin low to reset external h...

Page 25: ...IR S0EIR ASC0 receive error interrupt request flags S0CON S0REN ASC0 receiver enable flag TFR TFR 15 14 13 Class A trap flags TFR TFR 7 6 3 2 1 0 Class B trap flags XPyIC y 1 3 XPyIR y 1 3 X Periphera...

Page 26: ...ommon address space The ST10R272L provides a total addressable memory space of 16MBytes This address space is arranged as 256 segments of 64KBytes each and each segment is subdivided into four data pa...

Page 27: ...addresses Words are stored in ascending memory locations with the low byte at an even byte address followed by the high byte at the next odd byte address Double words code only are stored in ascending...

Page 28: ...CE0h 00 FCFFh and the bit addressable space 00 FD00h 00 FDFFh The internal special function registers SFR are in the address range 00 FE00h 00 FFFFh and extended special function registers ESFR are in...

Page 29: ...se sequential boundary crossing from internal RAM to the SFR area is not supported and causes erroneous results Figure 6 Internal RAM and SFR areas XSSP Data Page 0 Data Page 1 Data Page 2 Data Page 3...

Page 30: ...hip RAM is accessed via the Stack Pointer SP register The stack grows downward from higher towards lower RAM address locations Only word accesses are supported by the system stack A stack overflow STK...

Page 31: ...bit in the currently active register bank can be accessed individually The ST10R272L supports fast register bank context switching Multiple register banks can physically exist within the internal RAM...

Page 32: ...urce and destination pointers selected by the specified PEC channel number is accessed independently of the current DPP register contents Also the locations referred to by these pointers are accessed...

Page 33: ...address word SFRs and their respective low bytes However this does not work for the respective high bytes Writing to any byte of an SFR causes the non addressed complementary byte to be cleared The u...

Page 34: ...pied by internal memory areas All addresses which are not used for on chip RAM registers or internal Xperipherals may reference external memory locations through the External Bus Interface Four memory...

Page 35: ...dress is implicitly divided into equally sized blocks of different granularity and into logical memory areas Crossing the boundaries between these blocks code or data or areas requires special attenti...

Page 36: ...ake sure that the highest used code location of a segment contains an unconditional branch instruction to the respective following segment Data Pages are contiguous blocks of 16KByte each They are ref...

Page 37: ...sing one register bank may overlap others A system stack of up to 1024 bytes is provided as a storage for temporary data The system stack is allocated in the on chip RAM area and it is accessed by the...

Page 38: ...pt vector jump table PEC interrupt processing steals one machine cycle from the current CPU activity to perform a single data transfer via the on chip Peripheral Event Controller PEC System errors det...

Page 39: ...and if required the operand addresses are calculated and respective operands are fetched For all instructions which implicitly access the system stack the SP register is either decremented or incremen...

Page 40: ...tion which has already been fetched is not usually the instruction which must be decoded next Thus at least one additional machine cycle is normally required to fetch the branch target instruction Thi...

Page 41: ...ns the target instruction of a jump cache instruction JMPA JMPR JB JBC JNB JNBS is also stored in the cache For subsequent execution of the same jump cache instruction the jump target instruction is n...

Page 42: ...on which calculates a physical GPR operand address via the CP register is not usually capable of using a new CP value which is to be updated by an immediately preceding instruction Therefore to make s...

Page 43: ...register value without erroneously performed stack accesses at least one instruction must be inserted between an explicitly SP writing and any subsequent SP using instructions as shown in the followi...

Page 44: ...sequences should not begin directly after the instruction disabling interrupts as shown in the following example Note A delay of one instruction also applies to the enabling of the interrupt system i...

Page 45: ...ss area should be inserted Code accesses to the new address area should be made after an absolute branch to this area Note As a rule instructions that change external bus properties should not be exec...

Page 46: ...ps internally use a read modify write sequence that accesses the whole word This method has several consequences Bits can only be modified within the internal address areas i e internal RAM and SFRs E...

Page 47: ...the various instructions and the specific exceptions can be found in the ST10 Family Programming Manual The table below shows the minimum execution times required to process an instruction fetched fro...

Page 48: ...s The PSW SP and MDC registers can be modified not only explicitly by the programmer but also implicitly by the CPU during normal instruction processing Note that any explicit write request via softwa...

Page 49: ...uce the power supply current PWDCFG Power Down Mode Configuration Control 0 Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low otherwise the instruction has no ef...

Page 50: ...code address space is restricted to 64 KBytes segment 0 and therefore 16 bits are sufficient to represent all code addresses For implicit stack operations CALL or RET the CSP register is totally igno...

Page 51: ...es it possible to use a bigger virtual stack than this dedicated RAM area These techniques as well as the encoding of bitfield STKSZ are described in more detail in SYSTEM PROGRAMMING on page 303 Proc...

Page 52: ...FFh for the word data type or from 80h to 7Fh for the byte data type For Boolean bit operations with only one operand the N flag represents the previous state of the specified bit For Boolean bit oper...

Page 53: ...ag indicates an arithmetic overflow For multiplication and division the V flag is set to 1 if the result cannot be represented in a word data type otherwise it is cleared Note that a division by zero...

Page 54: ...t service routine when a multiply or divide ALU operation is interrupted before completion Depending on the state of the MULIP bit the hardware decides whether a multiplication or division must be con...

Page 55: ...ch while the upper 8 bits are reserved for future use Code memory addresses are generated by directly extending the 16 bit content of the IP register by the contents of the CSP register as shown in Fi...

Page 56: ...ing active simultaneously at run time The lower 10 bits of each DPP register select one of the 1024 possible 16 Kbyte data pages and the upper 6 bits are reserved for future use The DPP registers give...

Page 57: ...SFR Reset Value 0000h DPP1 FE02h 01h SFR Reset Value 0001h DPP2 FE04h 02h SFR Reset Value 0002h DPP3 FE06h 03h SFR Reset Value 0003h Data paging is performed by concatenating the lower 14 bits of an i...

Page 58: ...ny instruction which is capable of modifying an SFR Due to the Internal Instruction Pipeline a new DPP value can not be used for the operand address calculation of an instruction immediately following...

Page 59: ...lue can not be used for GPR address calculation of the instruction immediately following the instruction updating the CP register The switch context instruction SCXT saves the content of the CPregiste...

Page 60: ...s are possible GPRs used as indirect address pointers are always accessed wordwise For some instructions only the first four GPRs can be used as indirect address pointers These GPRs are specified by s...

Page 61: ...ver data is to be popped from the stack Therefore the system stack grows from higher toward lower memory locations Since the least significant bit the SPregister is tied to 0 and bits 15 through 12 ar...

Page 62: ...1 by hardware the STKOV register can only contain values from F000h to FFFEh The Stack Overflow Trap entered when SP STKOV may be used in two different ways Fatal error indication treats the stack ov...

Page 63: ...ck Underflow Trap entered when SP STKUN may be used in two different ways Fatal error indication treats the stack underflow as a system error through the associated trap service routine Automatic syst...

Page 64: ...performed within the interrupt service routine registers MDH MDL and MDC must be saved to avoid erroneous results A detailed description of how to use the MDH register for programming multiply and di...

Page 65: ...struction When a division or multiplication is interrupted before completion and the multiply divide unit is required the MDC register must first be saved with registers MDH and MDL to be able to rest...

Page 66: ...ction capable of addressing a SFR The constant ones register ONES All bits of this bit addressable register are fixed to 1 by hardware This register is read only Register ONES can be used as a registe...

Page 67: ...n capable of addressing an SFR ZEROS FF1Ch 8Eh SFR Reset Value 0000h ONES FF1Eh 8Fh SFR Reset Value FFFFh 0 0 0 0 0 5 4 3 2 1 0 11 10 9 8 7 6 15 14 13 12 r r r r r r 0 0 0 r 0 0 0 0 0 0 0 0 r r r r r...

Page 68: ...es enable the CPU to supply the MAC with up to 2 operands per instruction cycle MAC instructions multiply multiply accumulate 32 bit signed arithmetic operations and the CoMOV transfer instruction hav...

Page 69: ...erations 16 x 16 signed unsigned parallel multiplier 40 bit signed arithmetic unit with automatic saturation mode 40 bit accumulator 8 bit left right shifter Scaler one bit left shifter Data limiter F...

Page 70: ...red operand addresses are calculated and the resulting operands are fetched IDX and GPR pointers are post modified if necessary Figure 17 MAC architecture Operand2 Operand1 Control Unit Repeat Unit ST...

Page 71: ...modes have been added to supply the MAC with two new operands per instruction cycle These allow indirect addressing with address pointer post modification Double indirect addressing requires two poin...

Page 72: ...epending on the post modification of IDXi It is obtained by the reverse operation than the one used to calculate the new value of IDXi The following table shows these rules Rwn stands for Rwn Rwn Rwn...

Page 73: ...ing two 16 bit signed 2 s complement fractional numbers if bit MP is set 5 2 4 40 bit signed arithmetic unit The arithmetic unit over 32 bits wide to allow intermediate overflow in a series of multipl...

Page 74: ...s explicitly reset by the user 40 bit overflow of the Accumulator sets the SV flag in MSW This flag is also a sticky flag 5 2 5 40 bit accumulator register The 40 bit Accumulator consists of three SFR...

Page 75: ...r zero If it is zero the instruction is terminated else the Repeat Count is decremented and the instruction is repeated During such a repeat sequence the Repeat Flag in MRW is set until the last execu...

Page 76: ...er during the interrupt routine otherwise the interrupt processing restarts when returning from the interrupt routine The MAC interrupt is implemented as a Class B hardware trap trap number Ah trap pr...

Page 77: ...ed only by multiply multiply accumulate instructions which specifies whether each operand is signed or unsigned In two s complement fractional format the N bit operand is represented using the 1 N 1 f...

Page 78: ...Reset Value 0000h QR1 F006h 03h ESFR Reset Value 0000h 5 3 2 Accumulator control registers The MAC unit SFRs include the 40 bit Accumulator MAL MAH and the low byte of MSW and 3 control registers the...

Page 79: ...pt Request Set when the MAC Unit generates an interrupt request SL Sticky Limit Flag Set when the result of a MAC operation is automatically saturated Also used for CoMIN CoMAX instructions to indicat...

Page 80: ...ple loading the Accumulator with MOV instructions will not modify the condition flags SV Sticky Overflow Flag Set when a MAC operation produces a 40 bit arithmetic overflow It remains set until it is...

Page 81: ...sk When set the SV Flag can generate a MAC interrupt request CM C Mask When set the C Flag can generate a MAC interrupt request MP Product Shift Mode When set enables the one bit left shift of the mul...

Page 82: ...le gives the address of the MAC registers in this CoReg addressing mode 5 4 MAC instruction set summary The following table gives an overview of the MAC instruction set All the mnemonics are listed wi...

Page 83: ...CoMACMRus CoMACsu CoMACMRsu CoMAC CoMACMR rnd CoMACu CoMACMRu rnd CoMACus CoMACMRus rnd CoMACsu CoMACMRsu rnd CoMAC rnd CoADD Rwn Rwm No CoMACu rnd CoADD2 IDXi Rwm Yes CoMACus rnd CoSUB Rwn Rwm Yes Co...

Page 84: ...ocks of data The ST10R272L has 8 PEC channels each of which offers fast interrupt driven data transfer capabilities Trap Functions Software interrupts are supported by means of the TRAP instruction in...

Page 85: ...caused the trap For the special software TRAP instruction the vector address is specified by the operand field of the instruction which is a seven bit trap number The reserved vector locations build...

Page 86: ...priority is higher than the current CPU priority in the PSW register External Interrupt 3 CC11IR CC11IE CC11INT 6Ch 1Bh GPT1 Timer 2 T2IR T2IE T2INT 88h 22h GPT1 Timer 3 T3IR T3IE T3INT 8Ch 23h GPT1...

Page 87: ...tion pointers which specify the PEC service channel task 6 1 4 Interrupt control registers All interrupt control registers are organized identically The lower 8 bits contain the source interrupt statu...

Page 88: ...e respective source occurs It is cleared automatically on entry into the interrupt service routine or on a PEC service For PEC services the interrupt request flag remains set if the COUNT field in the...

Page 89: ...gister contains zero In this case the request is serviced by normal interrupt processing Interrupt requests that are programmed to priority levels 13 through 1 will always be serviced by normal interr...

Page 90: ...e Figure 20 Priority levels and PEC channels Priority Level Type of Service ILVL GLVL COUNT 00h COUNT 00h 1 1 1 1 1 1 CPU interrupt level 15 group priority 3 PEC service channel 7 1 1 1 1 1 0 CPU inte...

Page 91: ...est sources will be acknowledged PEC transfers do not really interrupt the CPU but rather steal a single cycle so PEC services do not influence the ILVL field in the PSW Hardware Traps switch the CPU...

Page 92: ...ween two locations in segment 0 data pages 3 0 This is the fastest possible interrupt response and in many cases is sufficient to service a peripheral request e g serial channels etc Each channel is c...

Page 93: ...ers or no PEC service at all The table below summarizes how the COUNT field the interrupt requests flag IR and the PEC channel action depend on the previous content of COUNT The PEC transfer counter m...

Page 94: ...stination pointers specify the locations between which the data is to be moved A pair of pointers SRCPx and DSTPx is associated with each of the 8 PEC channels These pointers do not reside in specific...

Page 95: ...group of interrupt requests to be acknowledged disregarding all other requests The priority level of the source that wins the arbitration is compared against the CPU s current level The source is onl...

Page 96: ...L Each interrupt service routine within this class sets the CPU level to the highest interrupt priority within the class All requests from the same or any lower level will be blocked i e no request fr...

Page 97: ...tiplication or division is in progress when the interrupt request is acknowledged bit MULIP in the PSW register is set to 1 In this case the return location that is saved on the stack is not the next...

Page 98: ...nter CP on the system stack and loads CP with the immediate value New_Bank which selects a new register bank The service routine can now use its own registers This register bank is preserved when the...

Page 99: ...e of the pipeline replacing instruction N 1 and clearing the source s interrupt request flag to 0 Cycle 4 Saves PSW IP and CSP if segmented mode and fetches the first instruction I1 from the respectiv...

Page 100: ...ands are located there are a number of combinations Note however that only access conflicts contribute to the delay The following examples illustrate these delays The worst case interrupt response tim...

Page 101: ...ponse time is the time between the setting of the interrupt request flag of an enabled interrupt source to the start of the PEC data transfer This is 2 instruction cycles for the ST10R272L The PEC res...

Page 102: ...s the PEC response time due to pipeline related access priorities The following conditions must be considered Instruction fetch from an external location Operand read from an external location Result...

Page 103: ...positive a negative or both a positive and a negative external transition can be selected to cause an interrupt or PEC service request The edge selection is performed in the control register of the pe...

Page 104: ...tive transition to set the interrupt request flag and with CI 11b both a positive and a negative transition will set the request flag When the interrupt enable bit CRIE is set an interrupt request for...

Page 105: ...eld x 3 0 0 0 Fast external interrupts disabled standard mode 0 1 Interrupt on positive edge rising 1 0 Interrupt on negative edge falling 1 1 Interrupt on any edge rising or falling Register Address...

Page 106: ...RETI return from interrupt instruction to ensure correct operation Note The CPU level in the PSW register is not modified by the TRAP instruction so the service routine is executed on the same priorit...

Page 107: ...Interrupt NMI NMITRAP 00 0008h 02h II Stack Overflow STKOF STOTRAP 00 0010h 04h II Stack Underflow STKUF STUTRAP 00 0018h 06h II class B Hardware Traps Undefined opcode UNDOPC BTRAP 00 0028h 0Ah I Pr...

Page 108: ...on the lowest priority Bit Function ILLBUS Illegal External Bus Access Flag An external access has been attempted with no external bus defined ILLINA Illegal Instruction Access Flag A branch to an od...

Page 109: ...detected the NMI flag in register TFR is set and the CPU enters the NMI trap routine The IP value pushed on the system stack is the address of the instruction following the one after which normal pro...

Page 110: ...fault trap routine The protected instructions include DISWDT EINIT IDLE PWRDN SRST and SRVWDT The IP value pushed onto the system stack for the protection fault trap is the address of the instruction...

Page 111: ...ST10R272L INTERRUPT AND TRAP FUNCTIONS 110 320 6 9 12 MAC interrupt on condition User defined in the MCW register...

Page 112: ...e All port lines are bit addressable and all input output lines are individually bit wise programmable as inputs or outputs via direction registers except Port 5 The I O ports are true bidirectional p...

Page 113: ...ers a high impedance state The high level must then be provided by an external pullup device With this feature it is possible to connect several port pins together to a Wired AND configuration saving...

Page 114: ...put function of a pin is to be used the direction of this pin must be programmed for output DPx y 1 except for some signals that are used directly after reset and are configured automatically Otherwis...

Page 115: ...t There is one basic structure for all port lines with only an alternate input function Port lines with only an alternate output function however have different structures due to the way the direction...

Page 116: ...1h ESFR Reset Value 00h Bit Function P0X y Port data register P0H or P0L bit y Bit Function DP0X y Port direction register DP0H or DP0L bit y DP0X y 0 Port line P0X y is an input high impedance DP0X y...

Page 117: ...s can remain connected to the PORT0 pins also during normal operation however care has to be taken such that they do not disturb the normal function of PORT0 this might be the case for example if the...

Page 118: ...g data on PORT0 is read on the line Alternate Data Input While an external bus mode is enabled the user software should not write to the port output latch otherwise unpredictable results may occur Whe...

Page 119: ...hows the structure of a PORT0 pin 7 2 Port 1 The two 8 bit ports P1H and P1L represent the higher and lower part of PORT1 respectively Both halves of PORT1 can be written e g via a PEC transfer withou...

Page 120: ...l 16 port lines can be used for general purpose I O Bit Function P1X y Port data register P1H or P1L bit y Bit Function DP1X y Port direction register DP1H or DP1L bit y DP1X y 0 Port line P1X y is an...

Page 121: ...port output latch is disconnected from the internal bus and is switched to the line labeled Alternate Data Output via a multiplexer The alternate data is the 16 bit intrasegment address While an exte...

Page 122: ...register DP2 Each port line can be switched into push pull or open drain mode via the open drain control register ODP2 7 3 1 Alternate functions of port 2 Port 2 lines P2 11 P2 8 can serve as Fast Ext...

Page 123: ...ontrol register bit y ODP2 y 0 Port line P2 y output driver in push pull mode ODP2 y 1 Port line P2 y output driver in open drain mode Port 2 Pin Alternate Function P2 8 P2 9 P2 10 P2 11 EX0IN Fast Ex...

Page 124: ...ST10R272L PARALLEL PORTS 123 320 Figure 31 Port 2 I O and alternate functions Port 2 Alternate Function a General Purpose Fast External Interrupt Input P2 11 P2 10 P2 9 P2 8 EX3IN EX2IN EX1IN EX0IN...

Page 125: ...is 15 bit port is used for general purpose I O the direction of each line can be configured via the corresponding direction register DP3 Most port lines can be switched into push pull or open drain mo...

Page 126: ...r DP3 bit y DP3 y 0 Port line P3 y is an input high impedance DP3 y 1 Port line P3 y is an output Bit Function ODP3 y Port 3 Open Drain control register bit y ODP3 y 0 Port line P3 y output driver in...

Page 127: ...6 Toggle Output GPT2 Capture Input Timer 3 Toggle Output Timer 3 External Up Down Control Input Timer 4 Count Input Timer 3 Count Input Timer 2 Count Input ASC0 Transmit Data Output ASC0 Receive Data...

Page 128: ...the user must set the direction of the port line to output DP3 y 1 and must set the port output latch P3 y 1 Otherwise the pin is in its high impedance state when configured as input or the pin is st...

Page 129: ...e output function However its structure is slightly different see figure below because after reset the BHE or WRH function must be used depending on the system start up configuration In these cases th...

Page 130: ...t port If the SSP is disabled bit SSPEN cleared in SYSCON register Port 4 is used for general purpose I O the direction of each line can be configured via the corresponding direction register DP4 If t...

Page 131: ...ess lines are selected the alternate function of Port 4 may be necessary to access e g external memory directly after reset For this reason Port 4 will be switched to its alternate function automatica...

Page 132: ...n I O SSPCE0 Gen I O SSPDAT Gen I O SSPCLK Seg Address A16 Seg Address A17 Gen purpose I O Gen purpose I O Gen I O SSPCE1 Gen I O SSPCE0 Gen I O SSPDAT Gen I O SSPCLK Seg Address A16 Seg Address A17 S...

Page 133: ...MUX Write P4 y Read P4 y Enable Function Alternate 0 1 MUX Read DP4 y Write DP4 y Direction 1 Input Latch Clock Latch s u B l a n r e t n I P4 y y 3 0 VR02075C Output Buffer MUX 1 0 Alternate Data Ou...

Page 134: ...to P5 will be lost P5 FFA2h D1h SFR Reset Value XX h Figure 41 Block diagram of port 4 pin SSPDAT A22 Bit Function P5 y Port data register P5 bit y Read only VR02075D Output Buffer Latch Port Output...

Page 135: ...P5 12 P5 13 P5 14 P5 15 T6EUDTimer 6 external Up Down Control Input T5EUDTimer 5 external Up Down Control Input T6INTimer 6 Count Input T5INTimer 5 Count Input T4EUDTimer 4 external Up Down Control In...

Page 136: ...sponding direction register DP6 Each port line can be switched into push pull or open drain mode via the open drain control register ODP6 P6 FFCCh E6h SFR Reset Value 00h Figure 43 Block diagram of a...

Page 137: ...ed value can be read from bitfield CSSEL in register RP0H read only e g in order to check the configuration during run time Bit Function DP6 y Port direction register DP6 bit y DP6 y 0 Port line P6 y...

Page 138: ...6 1 P6 2 P6 3 P6 4 Gen purpose I O Gen purpose I O Gen purpose I O Gen purpose I O Gen purpose I O Chip select CS0 Chip select CS1 Gen purpose I O Gen purpose I O Gen purpose I O Chip select CS0 Chip...

Page 139: ...up device will not be active during Hold mode external pullup devices must be used in this case When entering Hold mode the CS lines are actively driven high for one CPU clock cycle then the output le...

Page 140: ...n register PSW When the bus arbitration signals are enabled via HLDEN also these pins are switched automatically to the appropriate direction Note that the pin drivers for HLDA and BREQ are automatica...

Page 141: ...et Value 0h Bit Function P7 y Port data register P7 bit y Bit Function DP7 y Port direction register DP7 bit y DP7 y 0 Port line P7 y is an input high impedance DP7 y 1 Port line P7 y is an output Bit...

Page 142: ...e below summarizes the alternate functions of Port 7 Port 7Pin Alternate Function P7 3 POUT3 PWM Channel 3 Output Table 23 Port 7 alternate functions Figure 48 Port 7 I O and Alternate Functions P7 3...

Page 143: ...ception is however that the port output latch value and the alternate data output are not ANDed but EXORed This feature inverts the alternate output by writing a 1 into the respective output latch Wit...

Page 144: ...ernate function of P3 12 BHE During reset and during Hold mode an internal pullup ensures an inactive high level on the WR WRL output READY READY Ready Input receives a control signal from an external...

Page 145: ...All VCC pins and all VSS pins must be con nected to the power supply and ground respectively VPP RPD Flash Programming Voltage for ST10F262 or Exit From Powerdown for all derivtives If a Fast External...

Page 146: ...gth waitstates READY control ALE RW delay These parameters are used for accesses within a specific address area which is defined via the corresponding register ADDRSELx The four pairs BUSCON1 ADDRSEL1...

Page 147: ...its port lines together with some control lines to build the external bus The bus configuration BTYP for the address windows BUSCON4 BUSCON1 is selected via software typically during the initializati...

Page 148: ...L multiplexes address and data a 16 bit data bus requires a word latch the least significant address line A0 is not relevant for word accesses The upper address lines An A16 are permanently output on...

Page 149: ...No address latches are required The EBC initiates an external access by placing an address on the address bus After a programmable period of time the EBC activates the respective command signal RD WR...

Page 150: ...s Reprogramming the BUSCON and or ADDRSEL registers allows to either change the bus mode for a given address window or change the size of an address window that uses a certain bus mode Reprogramming a...

Page 151: ...When an access code fetch or data is initiated the respective generated physical address defines if the access is made internally uses one of the address windows defined by ADDRSEL4 1 or uses the defa...

Page 152: ...bsequent byte accesses where the low byte is accessed first then the high byte The assembly of bytes to words and the disassembly of words into bytes is handled by the EBC and is transparent to the CP...

Page 153: ...ed as standard I O pin The BHE pin is implicitly used by the External Bus Controller to select one of two byte organized memory chips which are connected to the ST10R272L via a word wide external data...

Page 154: ...s and are driven active low for any access within the address area defined for the respective BUSCON register For any access outside this defined address area the respective CSx signal will go inactiv...

Page 155: ...hip mode when the first instruction is fetched Internal pullup devices hold the selected CS lines high during reset After the end of a reset sequence the pullup devices are switched off and the pin dr...

Page 156: ...defined via register pairs AD DRSELx BUSCONx which allow to access different resources with different bus character istics These address windows are arranged hierarchically where BUSCON4 overrides BU...

Page 157: ...alling edge are controlled by the ALECTLx bits in the BUSCON registers When bit ALECTL is set to 1 external bus cycles accessing the respective address window will have their ALE signal prolonged by h...

Page 158: ...ective memory or peripheral This access time is the total time required to move the data to the destination It represents the period of time during which the controller s signals do not change The ext...

Page 159: ...after deactivation of the read command RD The output of the next address on the external bus can be delayed for a memory or peripheral which needs more time to switch off its bus drivers by introducin...

Page 160: ...e falling edge of the command Without read write delay the falling edges of ALE and command s are coincident except for propagation delays With the delay enabled the command s become active half a CPU...

Page 161: ...e waitstates are not enough or where the response access time of a peripheral is not constant the ST10R272L provides external bus cycles that are terminated by a READY or READY input signal synchronou...

Page 162: ...hronous READY READY i e the READY READY signal is synchronized internally The Synchronous READY READY provides the fastest bus cycles but requires setup and hold times to be met The CLKOUT signal shou...

Page 163: ...or a peripheral access it may be delayed see example b in the figure above As memories tend to be faster than peripherals there should be no impact on system performance When using the READY READY fun...

Page 164: ...of these registers BUSCON4 BUSCON1 have an associated address select register ADDRSEL4 ADDRSEL1 which specifies up to four address areas and the individual bus characteristics within these areas All...

Page 165: ...bypassed the CPU clock is always driven by XTAL1 signal The PLL is turned off to reduce the power supply current PWDCFG Power Down Mode Configuration Control 0 Power Down Mode can only be entered duri...

Page 166: ...ined by the RDYPOL bit in the associated BUSCON register CLKEN System Clock Output Enable CLKOUT 0 CLKOUT disabled pin may be used for general purpose IO 1 CLKOUT enabled pin outputs the system clock...

Page 167: ...with falling edge of ALE MTT C0 RWD C0 RDY EN0 5 4 3 2 1 0 11 10 9 8 7 6 15 14 13 12 rw rw rw rw rw CSW EN0 BUS ACT0 rw ALE CTL0 rw rw CSR EN0 rw RDY POL0 rw MCTC BTYP MTT C1 RWD C1 RDY EN1 5 4 3 2 1...

Page 168: ...Bus Active Control 0 External bus disabled 1 External bus enabled within the respective address window see ADDRSEL RDYENx READY Input Enable 0 External bus cycle is controlled by bit field MCTC only...

Page 169: ...BUSCON1 within the complete address space Bit Function RGSZ Range Size Selection Defines the size of the address area controlled by the respective BUSCONx ADDRSELx register pair See table below RGSAD...

Page 170: ...esses inside the window The lower bits of the start address marked x are disregarded 9 4 3 Prioritizing address areas A prioritizing scheme is used to allow overlapping of address areas The ADDRSELs r...

Page 171: ...an overlapping among address areas defined via registers ADDRSEL3 and 4 is allowed The BUSCON0 register always has the lowest priority and its address area can be overlapped by any of the other ADDRSE...

Page 172: ...CS2 CS0 0 1 2 CS lines CS1 CS0 1 0 No CS lines at all 1 1 5 CS lines CS4 CS0 Default without pulldowns SALSEL Segment Address Line Selection Number of active segment address outputs 0 0 4 bit segment...

Page 173: ...dance floating PORT1 if used for the bus interface drives the address used last Port 4 the activated pins drives the segment address used last Port 6 drives the CS signal corresponding to the address...

Page 174: ...n after the arbitration mechanism has been switched off by clearing HLDEN All three pins are used for bus arbitration after bit HLDEN was set once 9 6 1 Entering the hold state Access to the ST10R272L...

Page 175: ...re The figure above shows the first chance that BREQ has to become active 9 6 2 Exiting the hold state The external bus master returns the access rights to the ST10R272L by driving the HOLD input high...

Page 176: ...e The ST10R272L provides an on chip interface the XBUS interface which allows to connect integrated customer application specific peripherals to the standard controller core The XBUS is an internal re...

Page 177: ...may be bytewide or wordwide with or without a separate address bus Interrupt nodes and configuration pins on PORT0 are provided for X Peripherals to be integrated Note If you plan to develop your own...

Page 178: ...t clock and pulse width resolution Figure 0 1 SFRs and port pins associated with PWM unit The pulse width modulation module operates on channel 3 of the PWM module This channel has a 16 bit up down co...

Page 179: ...a greater than or equal to comparison PWM Output Signal PT3 PW3 10 1 Operating Modes The PWM module provides three different operating modes Mode 0 standard PWM generation edge aligned PWM Mode 1 symm...

Page 180: ...reater than the contents of the pulse width shadow register The signal is switched back to a low level when the timer is reset to 0000h i e below the pulse width shadow register The period of the resu...

Page 181: ...related to the clearing of the timer Figure 65 Operation and output waveform in Mode 0 0 1 3 2 PW3 2 PW3 4 PW3 6 PW3 7 PW3 8 PW3 1 PW3 0 Duty Cycle 100 87 5 75 50 25 12 5 0 LSR LSR Latch Shadow Regist...

Page 182: ...nt pulses The PWM output signal is switched to a high level when the timer contents are equal to or greater than the contents of the pulse width shadow register while the timer is counting up The sign...

Page 183: ...mer contents are equal to or greater than the contents of the pulse width shadow register The signal is switched back to a low level when the timer is cleared i e is below the pulse width shadow regis...

Page 184: ...g on whether the pulse has already started i e the output is high or not i e the output is still low This multiple retriggering is always possible while the timer is running i e after the pulse has st...

Page 185: ...waveform in single shot mode 0 1 3 2 PW3 4 4 5 6 7 PP3 Period 7 PT3 Count Value 0 1 3 2 4 5 6 7 LSR PTR3 reset by Hardware PT3 stopped LSR Set PTR3 by Software for Next Pulse Set PTR3 by Software Pul...

Page 186: ...of counter PT3 rather than controlling the PWM output signal PT3 F036h 1Bh ESFR Reset Value 0000h The following table summarizes the PWM frequencies that result from various combinations of operating...

Page 187: ...the hardware compares the contents of the shadow register with the content of the counter PT3 The shadow register is loaded from the PW3 register at the beginning of every new PWM cycle or upon a wri...

Page 188: ...can be used for general purpose I O and the PWM signal can only be used to generate an interrupt request Bit Function PTR3 PWM Timer PT3 Run Control 0 Timer PT3 is disconnected from its input clock 1...

Page 189: ...t value The module interrupt for all channels is controlled by the PWM Module Interrupt Control register PWMIC This register is organized like any other standard interrupt control register shown herea...

Page 190: ...ss of how many channel interrupts were active However it will be set again if during execution of the service routine a new channel interrupt request is generated 10 4 PWM output signals In the ST10R2...

Page 191: ...zed below The portions of port and direction registers which are used by the GPT1for alternate functions are shaded Figure 68 SFRs and port pins associated with timer block GPT1 ODP3 Port 3 Open Drain...

Page 192: ...al position sensor signals A and B by their respective inputs TxIN and TxEUD Direction and count signals are internally derived from these two input signals so the contents of the respective timer Tx...

Page 193: ...Timer with Gate active high 1 X X Reserved Do not use this combination T3R Timer 3 Run Bit T3R 0 Timer Counter 3 stops T3R 1 Timer Counter 3 runs T3UD Timer 3 Up Down Control 1 1 For bits T3UD and T3U...

Page 194: ...an be changed regardless of whether the timer is running or not When pin T3EUD P3 4 is used as external count direction control input it must be configured as input i e its corresponding direction con...

Page 195: ...d T3M in the T3CON register to 000B In this mode T3 is clocked with the internal system clock CPU clock divided by a programmable pre scaler selected by bit field T3I The input frequency fT3 for timer...

Page 196: ...an alternate function of P3 6 To enable this operation pin T3IN P3 6 must be configured as input i e direction control bit DP3 6 must contain 0 If T3M 0 0 the timer is enabled when T3IN shows a low le...

Page 197: ...e a positive a negative or both a positive and a negative tran sition at this pin Bit field T3I in control the T3CON register selects the triggering transition see table below For counter operation pi...

Page 198: ...to interface to an incremental encoder T3 is clocked by Figure 72 Block diagram of core timer T3 in counter mode T3I Triggering Edge for Counter Increment Decrement 0 0 0 None Counter T3 is disabled...

Page 199: ...ording to the speed and the direction of the incremental encoder its contents therefore always represent the encoder s current position Figure 73 Core timer T3 in incremental interface mode T3I Trigge...

Page 200: ...gger a reset timer T3 e g via PEC transfer from ZEROS For incremental interface operation the following conditions must be met Bitfield T3M must be 110B Both pins T3IN and T3EUD must be configured as...

Page 201: ...control and input jitter is compensation Input jitter is compensation might occur if the sensor rests near to one of the switching points Level on respective other input T3IN Input T3EUD Input Rising...

Page 202: ...ode with the same options for the timer frequencies and the count signal as the core timer T3 In addition to these 3 counting modes the auxiliary timers can be concatenated with the core timer or they...

Page 203: ...rating Mode TxM Timer x Mode Control Basic Operating Mode 0 0 0 Timer Mode 0 0 1 Counter Mode 0 1 0 Gated Timer with Gate active low 0 1 1 Gated Timer with Gate active high 1 0 0 Reload Mode 1 0 1 Cap...

Page 204: ...d tables apply accordingly with one exception There is no output toggle latch and no alternate output pin for T2 and T4 Timers T2 and T4 in counter mode Counter mode for the auxiliary timers T2 and T4...

Page 205: ...lock source for an auxiliary timer in counter mode concatenates the core timer T3 with the respective auxiliary timer Depending on which transition of T3OTL is selected to clock the auxiliary timer th...

Page 206: ...y timers T2 and T4 is selected by setting bit field TxM in the respective register TxCON to 100B In reload mode the core timer T3 is reloaded with the contents of an auxiliary timer register triggered...

Page 207: ...he following functions can be performed If both a positive and a negative transition of T3OTL is selected to trigger a reload the core timer will be reloaded with the contents of the auxiliary timer e...

Page 208: ...tions The PWM signal can be output on T3OUT with T3OE 1 P3 3 1 and DP3 3 1 With this method the high and low time of the PWM signal can be varied in a wide range Note The output toggle latch T3OTL is...

Page 209: ...re mode It is recommended to keep this bit cleared TxI 2 0 Note When programmed for capture mode the respective auxiliary timer T2 or T4 stops independent of its run flag T2R or T4R Upon a trigger sel...

Page 210: ...interrupt control register for each of the three timers T2IC FF60h B0h SFR Reset Value 00h T3IC FF62h B1h SFR Reset Value 00h T4IC FF64h B2h SFR Reset Value 00h Note Please refer to the general Interr...

Page 211: ...utput on an alternate function port pin In addition T6 may be reloaded with the contents of CAPREL The toggle bit also supports the concatenation of T6 with auxiliary timer T5 while concatenation of T...

Page 212: ...it Function T6I Timer 6 Input Selection Depends on the Operating Mode see respective sections 2n n 2 9 2n n 2 9 T5EUD T5IN CPUClock CPUClock T6IN T6EUD T5 Mode Control T6 Mode Control GPT2Tim er T5 GP...

Page 213: ...mer Counter 6 stops T6R 1 Timer Counter 6 runs T6UD Timer 6 Up Down Control 1 T6UDE Timer 6 External Up Down Enable 1 T6OE Alternate Output Function Enable T6OE 0 Alternate Output Function Disabled T6...

Page 214: ...With a high level at T6EUD the timer is counting down If T6UD 1 a high level at pin T6EUD specifies counting up and a low level specifies counting down The count direction can be changed regardless o...

Page 215: ...n be used as general purpose IO pin In addition T6OTL can be used in conjunction with the timer over underflows as an input for the counter function of the auxiliary timer T5 For this purpose the stat...

Page 216: ...and to the auxiliary timer T5 in timer and gated timer mode Refer to the device datasheet for a table of timer input frequencies resolution and periods for the range of pre scaler options Figure 84 B...

Page 217: ...vel at this pin stops the timer If T6M 0 1 pin T6IN must have a high level in order to enable the timer In addition the timer can be turned on or off by software using bit T6R The timer will only run...

Page 218: ...cles before it changes 11 2 2 GPT2 Auxiliary Timer T5 The auxiliary timer T5 can be configured for timer gated timer or counter mode with the same options for the timer frequencies and the count signa...

Page 219: ...on Depends on the Operating Mode see respective sections T5M Timer 5 Mode Control Basic Operating Mode 0 0 Timer Mode 0 1 Counter Mode 1 0 Gated Timer with Gate active low 1 1 Gated Timer with Gate ac...

Page 220: ...gly with one exception There is no output toggle latch and no alternate output pin for T5 Timer T5 in counter mode Counter mode for the auxiliary timer T5 is selected by setting bit field T5M in regis...

Page 221: ...Depending on which transition of T6OTL is selected to clock the auxiliary timer this concatenation forms a 32 bit or a 33 bit timer counter 32 bit Timer Counter If both a positive and a negative trans...

Page 222: ...transitions on input T3IN or input T3EUD or both inputs T3IN and T3EUD The active edge is controlled by bit field CI in register T5CON The maximum input frequency for the capture trigger signal at CA...

Page 223: ...med or not If T5SC 0 the input pin CAPIN can still be used to clear timer T5 or as an external interrupt input This interrupt is controlled by the CAPREL interrupt control register CRIC GPT2 capture r...

Page 224: ...r CAPREL in capture and reload mode Since the reload function and the capture function of register CAPREL can be enabled individually by bits T5SC and T6SR the two functions can be enabled simultaneou...

Page 225: ...s contains the correct time between two events measured in timer T5 increments Timer T6 which runs in timer mode counting down with a frequency of e g fCPU 4 uses the value in register CAPREL to perfo...

Page 226: ...CAPIN interrupt request flag CRIR in register CRIC is set Setting any request flag will cause an interrupt to the respective timer or CAPREL interrupt vector T5INT T6INT or CRINT or trigger a PEC serv...

Page 227: ...register contains control bits for mode and error check selection and status flags for error identification A transmission is started by writing to the write only transmit buffer register S0TBUF by a...

Page 228: ...of the serial interface S0CON FFB0h D8h SFR Reset Value 0000h Bit Function S0M ASC0 Mode Control 0 0 0 8 bit data synchronous operation 0 0 1 8 bit data async operation 0 1 0 Reserved Do not use this...

Page 229: ...1 Must be reset by software S0FE Framing Error Flag Set by hardware on a framing error S0FEN 1 Must be reset by software S0OE Overrun Error Flag Set by hardware on an overrun error S0OEN 1 Must be res...

Page 230: ...ta mode The parity error flag S0PE will be set along with the error interrupt request flag if a wrong parity bit is received The parity bit itself will be stored in bit S0RBUF 7 9 bit data frames cons...

Page 231: ...errupted by a data byte An address byte will interrupt all slaves operating in 8 bit data wake up bit mode so each slave can examine the 8 LSBs of the received character the address The addressed slav...

Page 232: ...0 when the start bit is sampled the receive circuit is reset and waits for the next 1 to 0 transition at pin RXD0 If the start bit proves valid the receive circuit continues sampling and shifts the in...

Page 233: ...t and S0REN 0 half duplex no reception Data transmission is double buffered When the transmitter is idle the transmit data loaded into S0TBUF is immediately moved to the transmit shift register thus f...

Page 234: ...buffer register at the time the reception of the next byte is complete both the error interrupt request flag S0EIR and the overrun error status flag S0OE will be set provided the overrun check has be...

Page 235: ...egister S0BG is the dual function Baud Rate Generator Reload register Reading S0BG returns the content of the timer bits 15 13 return zero while writing to S0BG always updates the reload register bits...

Page 236: ...ck speed 12 5 ASC0 interrupt control Four bit addressable interrupt control registers are provided for serial channel ASC0 Register S0TIC controls the transmit interrupt S0TBIC controls the transmit b...

Page 237: ...terrupts For normal operation i e apart from the error interrupt the ASC0 provides three interrupt requests to control data exchange via this serial channel S0TBIR activated when data is moved from S0...

Page 238: ...for the handler to respond to the transmitter interrupt request in synchronous mode it is not possible at all Using the transmit buffer interrupt S0TBIR to reload transmit data allows the time to tra...

Page 239: ...connected to the SSP for transfer The SSP transmits 1 3 bytes or receives 1 byte after sending 1 3 bytes synchronously to a shift clock which is generated by the SSP The SSP can start shifting with th...

Page 240: ...e disable control for the SSP module This bit is named XSSPEN Xperipheral SSP ENable Control After reset XSSPEN is set to 0 and the SSP is disabled The four upper pins of Port4 can be used for segment...

Page 241: ...operation for the SSP Figure 98 Synchronous serial port register XP1IC SSPTB0 SSPTB1 SSPTB2 SSPRB0 Data Registers 8 bit registers Control Registers Interrupt Control SSPTB0 SSPCON0 SSPTB SSPTB SSPRB...

Page 242: ...ages Improper use for read operations may cause line conflicts among several selected slaves SSPCM SSP Continuous Mode Selection 0 Single Transfer Mode Chip enable line deactivated after end of transf...

Page 243: ...n The figure below is a summary 13 2 2 SSP Control Register 1 SSPCON1 This register contains all bits which are required to configure the output lines of the SSP It contains control bits which are nor...

Page 244: ...1 SSPCEN1 Polarity Control Bit 0 Inactive Chip Enable line is low active level is high 1 Inactive Chip Enable line is high active level is low SSPCKO SSP Clock Line Output SSPCLK Control Bit 0 Clock...

Page 245: ...ring initialization while the clock line polarity and active edge might be switched between transfers to different peripheral slaves This can be handled by a write to only one control register SSPCON0...

Page 246: ...a write operation of the SSP The length of the transfer is determined through which transmit buffers were written to prior to the transfer Internal flags TBx_Full are used for this purpose These flags...

Page 247: ...rite operation controlled through transmit buffer full signal Transmit Buffers written Transfer length Transfer sequence SSPTB2 SSPTB1 SSPTB0 24 bit 3 byte transfer SSPTB2 SSPTB1 SSPTB0 SSPTB1 SSPTB2...

Page 248: ...tes in the Transmit Buffers After writing to SSPTB0 first the content of the transmit buffers are shifted out Then the data line SSPDAT is switched to input high impedance After a gap of one bit clock...

Page 249: ...s However if no transfer is in progress or the SSP is not used at all the polarity and output control bit can be used to perform general purpose output functions on the pins SSPCLK SSPCE0 and SSPCE1...

Page 250: ...writes to the slave device The gap between the transfers is application dependent since the CPU first has to react on the interrupt request at the end of one transfer and rewrite the transmit buffer r...

Page 251: ...in register XP1IC is set This can cause the following effects an interrupt to the XP1INT interrupt vector trigger a PEC service if the interrupt enable bit XP1IE in register XP1IC is set poll the XP1...

Page 252: ...as accesses to the external bus SSP accesses cannot be executed in parallel to external instruction fetches or data read writes but are arbitrated and inserted into the external bus access stream How...

Page 253: ...RSELx registers except that it uses the reduced address ranges which are defined for XBUS Peripherals With the mask programmed value shown above the following options are selected Fixing the SSP addre...

Page 254: ...Port 0 Port 1 Port 4 and Port 6 can be used for general purpose I O When bit VISIBLE in register SYSCON is set then accesses to the SSP can be made visible to the external world To do so one of the BU...

Page 255: ...executed in this mode if bit VISIBLE in register SYSCON is cleared In this case an access to the SSP is completely invisible to the external world If bit VISIBLE is set then SSP accesses have to wait...

Page 256: ...og Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset The Watchdog Timer is a 16 bit timer clocked with th...

Page 257: ...ill pull the external reset indication pin RSTOUT low It differs from a software or external hardware reset in that bit WDTR watchdog timer reset indication flag of register WDTCON will be set A hardw...

Page 258: ...be programmed in register WDTCON The period PWDT between servicing the watchdog timer and the next overflow can therefore be determined by the following formula Refer to the device datasheet for a ta...

Page 259: ...rogram execution from the memory location 00 0000h in code segment zero When a reset other than asynchronous reset is initiated pending internal hold states are cancelled and the current internal acce...

Page 260: ...ronized before exiting the reset condition Therefore only the entry of the this hardware reset is asynchronous An asynchronous hardware reset is triggered when a low logic level on RSTIN and RPD Vpp p...

Page 261: ...the other to RPD Vpp pin is sufficient for an automatic power on reset RSTIN may also be connected to the output of other logic gates When reset sequence is finished the RPD Vpp capacitor will be cha...

Page 262: ...ance RSTOUT is driven After RSTIN negation is detected a short transition period approximately 6 CPU clock cycles elapses during which pending internal hold states are cancelled and the current intern...

Page 263: ...clock cycles if the PLL is bypassed and the prescaler is on fCPU fXTAL 2 else it is 4 CPU clock cycles Figure 109 Synchronous warm reset external low pulse on RSTIN shorter than reset sequence CPU Cl...

Page 264: ...operation and 2 0V for 3 3V operation the asynchronous reset is then immediately entered Figure 110 Synchronous warm reset external low pulse on RSTIN longer than reset sequence CPU Clock RSTIN Intern...

Page 265: ...en charge the capacitor C Note that an internal pull down device on RPD Vpp pin is turned on when RSTIN pin is low and causes the external capacitor C to begin discharging at a typical rate of 100 A t...

Page 266: ...the voltage above VIL for short low pulses applied on RSTIN pin Figure 10 5 shows an example of a system reset circuit In this example R1C1 external circuit is only used to generate power up or manua...

Page 267: ...hdog timer reset When the watchdog timer is not disabled during the initialization or serviced regularly during program execution is will overflow and trigger the reset sequence Other than hardware an...

Page 268: ...us and control signals are activated immediately after the reset sequence according to the configuration latched from PORT0 so either external accesses can takes place or the external control signals...

Page 269: ...synchronously upon software or watchdog reset 3 The reset condition ends here The ST10R272L starts program execution 4 Activation of the IO pins is controlled by software 5 Execution of the EINIT ins...

Page 270: ...eted It will be clocked with the internal system clock divided by 2 and its default reload value is 00h so a watchdog timer overflow will occur 131072 CPU clock cycles after completion of the internal...

Page 271: ...rivers are switched to the high impedance state This ensures that the ST10R272L and external devices will not try to drive the same pin to different levels Pin ALE is held low through an internal pull...

Page 272: ...vector in the trap interrupt vector table the reset vector 4 words locations 00 0000h through 00 0007h are provided in this table to start the initialization after reset As a rule this location holds...

Page 273: ...size etc must be selected before the execution of EINIT 15 10 1 System start up configuration Although most of the programmable features of the ST10R272L are either selected during the initialization...

Page 274: ...configuration options The default modes refer to pins at high level i e without external pulldown devices connected The above note on reserved pins remains applicable 15 10 2 Emulation mode When low...

Page 275: ...n Adapt Mode 15 10 4 System clock configuration Pins P0H 7 to P0H 5 CLKSEL selects the system clock configuration at reset The system clock CPU Clock can be selected to be 0 5 1 2 2 5 3 4 or 5 times t...

Page 276: ...H Depending on the system architecture the required address space is chosen and accessible right from the start so the initialization routine can directly access all locations without prior programmin...

Page 277: ...terpret the format A word register looks like this Elements REG_NAME A16h A8h E SFR Reset Value h A byte register looks like this REG_NAME Name of this register A16 A8 Long 16 bit address Short 8 bit...

Page 278: ...R2 CP 4 F2h CPU General Purpose Word Register R2 UUUUh R3 CP 6 F3h CPU General Purpose Word Register R3 UUUUh R4 CP 8 F4h CPU General Purpose Word Register R4 UUUUh R5 CP 10 F5h CPU General Purpose Wo...

Page 279: ...F1h CPU General Purpose Byte Register Rh0 UUh RL1 CP 2 F2h CPU General Purpose Byte Register RL1 UUh RH1 CP 3 F3h CPU General Purpose Byte Register RH1 UUh RL2 CP 4 F4h CPU General Purpose Byte Regis...

Page 280: ...4 FEh CPU General Purpose Byte Register RL7 UUh RH7 CP 14 FFh CPU General Purpose Byte Register RH7 UUh Name Physical Address 8 Bit Address Description Reset Value ADDRSEL1 FE18h 0Ch Address Select Re...

Page 281: ...H b F106h E 83h P1h Direction Control Register 00h DP2 b FFC2h E1h Port 2 Direction Control Register 0 h DP3 b FFC6h E3h Port 3 Direction Control Register 0000h DP4 b FFCAh E5h Port 4 Direction Contro...

Page 282: ...Divide Register High Word 0000h MDL FE0Eh 07h CPU Multiply Divide Register Low Word 0000h MRW b FFDAh EDh MAC Unit Repeat Word 0000h MSW b FFDEh EFh MAC Unit Status Word 0200h ODP2 b F1C2h E E1h Port...

Page 283: ...Register 0000h PECC6 FECCh 66h PEC Channel 6 Control Register 0000h PECC7 FECEh 67h PEC Channel 7 Control Register 0000h PP3 F03Eh E 1Fh PWM Module Period Register 3 0000h PSW b FF10h 88h CPU Program...

Page 284: ...Transmit Interrupt Control Regis ter 0000h SP FE12h 09h CPU System Stack Pointer Register FC00h SSPCON0 EF00h X SSP Control Register 0 0000h SSPCON1 EF02h X SSP Control Register 1 0000h SSPRTB EF04h...

Page 285: ...IC b FF66h B3h GPT2 Timer 5 Interrupt Control Register 0000h T6 FE48h 24h GPT2 Timer 6 Register 0000h T6CON b FF48h A4h GPT2 Timer 6 Control Register 0000h T6IC b FF68h B4h GPT2 Timer 6 Interrupt Cont...

Page 286: ...Module Period Register 3 0000h F078h E IDPROG 3Ch Programming Voltage Identifier Register Refer to Data Sheetor Errata Sheet for val ues F07Ah E IDMEM 3Dh On chip Memory Identifier Register F07Ch E ID...

Page 287: ...bits 0002h FE06h DPP3 03h CPU Data Page Pointer 3 Register 10 bits 0003h FE08h CSP 04h CPU Code Segment Pointer Register read only 0000h FE0Ch MDH 06h CPU Multiply Divide Register High Word 0000h FE0...

Page 288: ...rate generator reload reg 0000h FEC0h PECC0 60h PEC Channel 0 Control Register 0000h FEC2h PECC1 61h PEC Channel 1 Control Register 0000h FEC4h PECC2 62h PEC Channel 2 Control Register 0000h FEC6h PE...

Page 289: ...ant Value 1 s Register read only FFFFh FF30h PWMCON0 b 98h PWM Module Control Register 0 0000h FF32h PWMCON1 b 99h PWM Module Control Register 1 0000h FF40h T2CON b A0h GPT1 Timer 2 Control Register 0...

Page 290: ...h FFACh TFR b D6h Trap Flag Register 0000h FFAEh WDTCON D7h Watchdog Timer Control Register 000xh2 FFB0h S0CON b D8h Serial Channel 0 Control Register 0000h FFC0h P2 b E0h Port 2 Register 4 bits 0 h F...

Page 291: ...with its revision a internal memory and size identifier programming voltage description FFDCh MCW EEh MAC Unit Control Word 0000h FFDEh MSW b EFh MAC Unit Status Word 0200h 1 The system configuration...

Page 292: ...on REVID Device Revision Identifier Refer to datasheet for values CHIPID Device Identifier Refer to datasheet for values Bit Function MEMSIZE Internal Memory Size Refer to datasheet for values MEMTYP...

Page 293: ...ge for FLASH devices is calculated using the formula Vdd 20 PROGVDD 256 V Refer to datasheet for values PROGVPP Programming Vpp Voltage Vpp voltage for FLASH devices is calculated using the formula Vp...

Page 294: ...rate normally only the CPU operation is halted Idle Mode is entered AFTER the IDLE instruction has been executed AND the instruction before IDLE has completed all stages of the pipeline This guarantee...

Page 295: ...will always be entered Any interrupt request whose individual Interrupt Enable flag is set before Idle Mode is entered terminates Idle Mode regardless of the current CPU priority The CPU will not go b...

Page 296: ...on is effective only if the NMI Non Maskable Interrupt pin is externally pulled low while PWRDN is executed The microcontroller enters Power Down mode after the PWRDN instruction has completed Protect...

Page 297: ...orts to their default state but does not change the contents of the internal RAM The initialization routine executed upon reset checks the identification flag or bit pattern within RAM to determine wh...

Page 298: ...able bit bit CCxIE in the respective CCxIC register need not to be set to bring the device out of Power Down mode An external RC circuit must be connected on the Vpp RPD pin as shown in the following...

Page 299: ...rns on an internal weak pull down on the Vpp RPD pin to discharge the capacitor C1 The discharging of the external capacitor provides a delay for the oscillator and PLL circuits to stabilize before th...

Page 300: ...e below If the interrupt was disabled the device executes the instruction following PWRDN instruction and the Interrupt Request Flag bit CCxIR in the respective CCxIC register remains set until it is...

Page 301: ...stabilization time then use the following formula to calculate the C value where Examples Figure 119 Simplified Powerdown Exit Circuitry C is the external capacitor on Vpp RPD in F TDIS is the worst...

Page 302: ...ion of a port pin is used by a peripheral the state of the pin is determined by the operation of the peripheral Port pins which are used for bus control functions go into that state which represents t...

Page 303: ...ed buses with 8 bit data bus A15 A8 2 Float PORT1 Last Address 3 Port Latch Data 3 For demultiplexed buses Last Address 3 Port Latch Data Port 4 Port Latch Data Last segment Port Latch Data Last segme...

Page 304: ...ructions can access the PSW register so instructions such as CLEAR CARRY or ENABLE INTERRUPTS are NOT required External Memory Data Access does not require special instructions to load data pointers o...

Page 305: ...only Bytes must either be converted to words or the respective other byte must be disregarded Register SP can only be loaded with even byte addresses The LSB of SP is always 0 Detection of stack overf...

Page 306: ...rs very infrequently If this is not true for a given program environment this technique should not be used because of the overhead of flushing and filling The basic mechanism is the transformation of...

Page 307: ...FEh 00 F600h Note No circular stack SP 11 SP 0 Figure 120 Physical stack address generation MOV SP 0F802h Set SP before last entry of physical stack of 256 words SP F802h Physical stack address FA02h...

Page 308: ...inters are updated to reflect the newly allocated space on the internal stack Thus the user is free to write code without concern for the internal stack limits User programs are only affected by the e...

Page 309: ...to off load data from the system stack The user may push both bytes and words onto a user stack but is responsible for using the appropriate instructions when popping data from the specific user stack...

Page 310: ...d and POP instructions during execution of the subroutine Base plus offset indirect addressing permits access to parameters without popping the parameters from the stack during subroutine execution In...

Page 311: ...e of the System Stack for Local Registers It is possible to use the SP and CP to set up local subroutine register frames This allows subroutines to dynamically allocate local variables as needed withi...

Page 312: ...mode and the E end of table flag stored in the PSW decrease the number of overhead instructions executed in the loop The two examples below illustrate searching ordered tables and non ordered tables...

Page 313: ...oftware by setting or clearing user specific bits and conditionally branching based on these specific bits It is recommended that bit fields in control SFRs are updated using the BFLDH and BFLDL instr...

Page 314: ...de illegal bus access etc however will interrupt the ATOMIC sequence since it indicates a severe hardware problem The interrupt inhibit caused by an ATOMIC instruction becomes active immediately i e n...

Page 315: ...t addressing modes to the ESFR space for 1 4 instructions Additional registers can also be accessed this way The EXTPR and EXTSR instructions combine the DPP override mechanism with re direction to th...

Page 316: ...72L SYSTEM PROGRAMMING 315 320 Note Interrupt latencies may be increased when using locked code sequences PEC requests are not serviced during idle mode if the IDLE instruction is part of a locked seq...

Page 317: ...et Value FC00h 58 CRIC FF6Ah B5h SFR Reset Value 00h 225 CSP FE08h 04h SFR Reset Value 0000h 55 DP0H F102h 81h ESFR Reset Value 00h 115 DP0L F100h 80h ESFR Reset Value 00h 115 DP1H F106h 83h ESFR Rese...

Page 318: ...ue 0000h 80 MSW FFDEh EFh SFR Reset Value 0200h 78 ODP2 F1C2h E1h ESFR Reset Value 00 h 122 ODP3 F1C6h E3h ESFR Reset Value 0000h 125 ODP6 F1CEh E7h ESFR Reset Value 00h 136 ODP7 F1D2h E9h ESFR Reset...

Page 319: ...77 RP0H F108h 84h SFR Reset Value XXh 171 S0CON FFB0h D8h SFR Reset Value 0000h 227 S0EIC FF70h B8h SFR Reset Value 00h 236 S0RIC FF6Eh B7h SFR Reset Value 00h 236 S0TBIC F19Ch CEh ESFR Reset Value 00...

Page 320: ...T4IC FF64h B2h SFR Reset Value 00h 209 T5CON FF46h A3h SFR Reset Value 0000h 218 T5IC FF66h B3h SFR Reset Value 00h 225 T6CON FF48h A4h SFR Reset Value 0000h 211 T6IC FF68h B4h SFR Reset Value 00h 225...

Page 321: ...reviously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics The ST lo...

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