ST10R272L - GENERAL PURPOSE TIMER UNITS
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When a selected transition at the external input pin (CAPIN, T3IN, T3EUD) is detected, the
contents of the auxiliary timer T5 are latched into register CAPREL, and interrupt request
flag CRIR is set. With the same event, timer T5 can be cleared to 0000
H
. This option is
controlled by bit T5CLR in register T5CON. If T5CLR=‘0’, the contents of timer T5 are not
affected by a capture. If T5CLR=‘1’, timer T5 is cleared after the current timer value has
been latched into register CAPREL.
Note
Bit T5SC only controls whether a capture is performed or not. If T5SC=‘0’, the input
pin CAPIN can still be used to clear timer T5 or as an external interrupt input. This
interrupt is controlled by the CAPREL interrupt control register CRIC.
GPT2 capture/reload register CAPREL in reload mode
This 16-bit register can be used as a reload register for the core timer T6. This mode is
selected by setting bit T6SR=‘1’ in register T6CON. The event causing a reload in this mode
is an overflow or underflow of the core timer T6.
When timer T6 overflows from FFFFh to 0000h (when counting up) or when it underflows
from 0000h to FFFFh (when counting down), the value stored in register CAPREL is loaded
into timer T6. This will not set the interrupt request flag CRIR associated with the CAPREL
Figure 89 GPT2 register CAPREL in capture mode
