ST10R272L - SYSTEM RESET
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15.2
Synchronous hardware reset (warm reset)
A warm synchronous hardware reset is triggered when the reset input signal RSTIN is
latched low and the RPD/Vpp pin is high. To ensure the recognition of the RSTIN signal
(latching), it must be held low for at least 2 CPU clock cycles. Shorter RSTIN pulses may
trigger a hardware reset, if they coincide with the latch’s sample point.
The I/Os are immediately (asynchronously) set in high impedance, RSTOUT is driven
After RSTIN negation is detected, a short transition period (approximately 6 CPU clock
cycles) elapses, during which pending internal hold states are cancelled and the current
internal access cycle (if any) is completed.
External bus cycle is aborted. Then, the internal reset sequence starts for 512 CPU clock
cycles. During this reset sequence, RSTIN pin is driven low and internal reset signal is
asserted to reset the microcontroller in its default state.
After the reset sequence has been completed, the RSTIN input is sampled. When the reset
input signal is active at that time the internal reset condition is prolonged until RSTIN gets
inactive
