ST10R272L - CENTRAL PROCESSING UNIT
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Data Page Pointer Updating
An instruction, which calculates a physical operand address via a particular DPPn (n=0 to 3)
register, is not capable of using a new DPPn register value which is to be updated by an
immediately preceding instruction. To make sure that the new DPPn register value is used,
at least one instruction must be inserted between a DPPn-changing instruction and a
subsequent instruction which implicitly uses DPPn via a long or indirect addressing mode,
for example:
Explicit stack pointer updating
None of the RET, RETI, RETS, RETP or POP instructions are capable of correctly using a
new SP register value which is to be updated by an immediately preceding instruction.
Therefore, to use the new SP register value without erroneously performed stack accesses,
at least one instruction must be inserted between an explicitly SP-writing and any
subsequent SP-using instructions, as shown in the following example:
External memory access sequences
This effect only becomes noticeable when watching the external memory access sequences
on the external bus (e.g. by means of a Logic Analyzer). Different pipeline stages can,
simultaneously, put a request on the External Bus Controller (EBC). The sequence of
instructions processed by the CPU may diverge from the sequence of corresponding
I
n
:
MOV DPP0, #4
;select data page 4 via DPP0
I
n+1
:
....
;must not be an instruction using DPP0
I
n+2
:
MOV DPP0:0000h, R1
;move contents of R1 to address location 01’0000h (data page 4) supposed
;segmentation is enabled
I
n
:
MOV SP, #0FA40h
;select a new top of stack
I
n+1
:
....
;must not be an instruction popping operands from the system stack
I
n+2
:
POP R0
;pop word value from new top of stack into R0
