ST10R272L - ARCHITECTURAL OVERVIEW
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number of register banks is only restricted by the available internal RAM space. For easy
parameter passing, one register bank may overlap another.
A system stack of up to 512 words stores temporary data. It is located in the on-chip RAM
area, and is accessed by the CPU via the Stack Pointer (SP) register. Two separate SFRs
(STKOV and STKUN) are implicitly compared against the stack pointer value, on each stack
access, for the detection of a stack overflow or underflow.
Hardware detection of the selected memory space is placed at the internal memory
decoders. It allows the user to specify any address directly or indirectly, and obtain the
desired data without using temporary registers or special instructions.
For special function registers 1024 Bytes of address space are reserved. The standard
Special Function Register area (SFR) uses 512 bytes, and the Extended Special Function
Register area (ESFR) uses the other 512 bytes. (E)SFRs are word-wide registers used for
controlling and monitoring the on-chip units. Unused (E)SFR addresses are reserved for
future development.
2.2.3
External bus interface
All external memory accesses are performed by the External Bus Controller (EBC). It can be
programmed either to Single-Chip Mode when no external memory is required, or to one of
four different external memory access modes:
•
16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed
•
16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed
•
16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed
•
16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1, and data is input/output
on PORT0 or P0L, respectively. In the multiplexed bus modes, both addresses and data use
PORT0 for input/output.
Important timing characteristics of the external bus interface (memory cycle time, memory
tri-state time, length of ale and read write delay) have been made programmable, to give the
choice of a wide range of different types of memories and external peripherals. In addition,
up to 4 independent address windows may be defined (via register pairs ADDRSELx /
BUSCONx) to access different resources with different bus characteristics. These address
windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2
overrides BUSCON1. All accesses to locations not covered by these 4 address windows are
controlled by BUSCON0. Up to 5 external CS signals (4 windows plus default) can be
generated to save external glue logic. Access to very slow memories is supported by the
‘Ready’ function.