ST10R272L - EXTERNAL BUS INTERFACE
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A READY/READY signal (especially asynchronous READY/READY) that has been activated
by an external device may be deactivated in response to the trailing (rising) edge of the
respective command (RD or WR).
Note
When the READY/READY function is enabled for a specific address window, each
bus cycle within this window must be terminated with an active READY/READY
signal. Otherwise the controller hangs until the next reset. A time-out function is
only provided by the watchdog timer.
Combining the READY function with predefined waitstates is advantageous in two
cases:
•
Memory components with a fixed access time and peripherals operating with READY/
READY may be grouped into the same address window. The (external) waitstate control
logic in this case would activate READY/READY either upon the memory’s chip select or
with the peripheral’s READY/READY output. After the predefined number of waitstates
the ST10R272L will check its READY/READY line to determine the end of the bus cycle.
For a memory access it will be low already (see example a in the figure above), for a
peripheral access it may be delayed (see example b in the figure above). As memories
tend to be faster than peripherals, there should be no impact on system performance.
•
When using the READY/READY function with so-called “normally-ready” peripherals, it
may lead to erroneous bus cycles, if the READY/READY line is sampled too early. These
peripherals pull their READY/READY output low, while they are idle. When they are
accessed, they deactivate READY/READY until the bus cycle is complete, then drive it
low again. If, however, the peripheral deactivates READY/READY after the first sample
point of the ST10R272L, the controller samples an active READY/READY and
terminates the current bus cycle, which, of course, is too early. By inserting predefined
waitstates the first READY/READY sample point can be shifted to a time, where the
peripheral has safely controlled the READY/READY line (e.g. after 2 waitstates in the
figure above).
9.3.6
Programmable chip select timing control
The position of the CSx lines can be changed. By default (after reset), the CSx lines change
half a CPU clock cycle after the rising edge of ALE. With the CSCFG bit set in the SYSCON
register (“Registers” on page 164), the CSx lines change with the rising edge of ALE,
therefore the CSx lines change at the same time as the address lines.
