ST10R272L - SYNCHRONOUS SERIAL PORT
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received from the slave is stored in register SSPRB0, and an internal flag RB0_Full is set.
Reading SSPRB0 through software clears this flag, and issues the next 8 clock pulses to
receive the next byte from the slave device. The time between the transfers depends again
on the application; the CPU has to react on the interrupt request and read register SSPRB0
in order to start the next transfer. This procedure continues until the mode is switched from
continuous mode back to normal mode. The chip enable lines will then be deactivated
immediately if no transfer is in progress or after the current transfer is completed.
13.2.10 Interrupt control for the SSP
At the end of a transfer in a read or write operation, the interrupt request flag XP1IR in
register XP1IC is set. This can cause the following effects:
•
an interrupt to the XP1INT interrupt vector,
•
trigger a PEC service if the interrupt enable bit XP1IE in register XP1IC is set,
•
poll the XP1IR flag by software. Note that when using polling technique, the software
must clear the XP1IR flag.
The timing for the interrupt request generation is such that the request bit is set one half bit
time after completion of the last data bit time. In reference to the normal mode, this is the
same time point where the chip enable line is deactivated. Note that the distinction between
a write or a read operation interrupt must be performed through software.
Figure 104 Read operation waveforms in continuous mode
SSPCLK
SSPDAT
SSPCE0, 1
RB0
Full
SSP
Interrupt
7
6
Data driven
to Slave
Data driven
from Slave
0
0
7
6
7
6
0
Data driven
from Slave
Read
RBO
Service
Interrupt
Service
Interrupt
Service
Interrupt
VR02084B
0
Byte n
Byte 1
Byte 0
Read
RBO
Read
RBO
Read
RBO
Data driven
from Slave
