ST10R272L - ARCHITECTURAL OVERVIEW
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The table below lists all the possible selections for the on-chip clock generator. Refer to the
device datasheet for the specific External Clock Input Range.
Figure 3 PLL block diagram
P0.15-13 (P0H.7-5)
CPU frequency f
CPU
=
f
XTAL
* F
Notes
1
1
1
F
XTAL
* 4
Default configuration
1
1
0
F
XTAL
* 3
1
0
1
F
XTAL
* 2
1
0
0
F
XTAL
* 5
0
1
1
F
XTAL
* 1
Direct drive
1
0
1
0
F
XTAL
* 1.5
0
0
1
F
XTAL
/ 2
CPU clock via 2:1 prescaler
0
0
0
F
XTAL
* 2.5
Table 1 CPU clock generation mechanisms
MUX
Oscillator
Circuit
PLL Circuit
f
PLL
= F * f
IN
reset sleep
Unlock
Reset
PWRDN
XP3INT
f
PLL
f
XTAL
P0H.7-5
f
CPU
XTAL2
XTAL1
Factor
Oscillator
Watchdog
Prescaler
(- 2)
MUX
P0H.6
MUX
