ST10R272L - GENERAL PURPOSE TIMER UNITS
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Note
A transition of the gate signal at pin T3IN does not cause an interrupt request.
Timer 3 in counter mode
Counter mode for the core timer T3 is selected by setting bit field T3M in the T3CON
register to ‘001
B
’. In counter mode timer T3 is clocked by a transition at the external input
pin T3IN, which is an alternate function of P3.6. The event causing an increment or
decrement of the timer can be a positive, a negative, or both a positive and a negative tran-
sition at this pin. Bit field T3I in control the T3CON register selects the triggering transition
(see table below).
For counter operation, pin T3IN/P3.6 must be configured as input, i.e. direction control bit
DP3.6 must be ‘0’. The maximum input frequency which is allowed in counter mode is
f
CPU
/
16. To ensure that a transition of the count input signal which is applied to T3IN is correctly
recognized, its level should be held high or low for at least 8 CPU clock cycles before it
changes.
Figure 71 Block diagram of core timer T3 in gated timer mode
T3IN = P3.6
T3EUD = P3.4
T3OUT = P3.3
x = 3
