ST10R272L - EXTERNAL BUS INTERFACE
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The memory cycle time wait states can be programmed in increments of one CPU clock
within a range from 0 to 15 (default after reset) via the MCTC fields of the BUSCON
registers. 15-<MCTC> waitstates will be inserted.
9.3.3
Programmable memory tri-state time
The time between two subsequent external accesses can be adjusted to account for the
tri-state time of the external device. The tri-state time defines, when the external device has
released the bus after deactivation of the read command (RD).
The output of the next address on the external bus can be delayed for a memory or
peripheral, which needs more time to switch off its bus drivers, by introducing a waitstate
after the previous bus cycle (see figure above). During this memory tri-state time wait state,
the CPU is not idle, so CPU operations will only be slowed down if a subsequent external
instruction or data fetch operation is required during the next instruction cycle.
The memory tri-state time waitstate requires one CPU clock and is controlled by the MTTCx
bits of the BUSCON registers. A waitstate will be inserted, if bit MTTCx is ‘0’ (default after
reset).
Figure 57 Memory cycle time
