ST10R272L - SYSTEM RESET
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held low until the CPU clock signal is available (about 10...50 ms to allow the on-chip
oscillator to stabilize).
The input RSTIN provides an internal pullup device equalling a resistor of 50 Kohms to 150
KOhms (the minimum reset time must be determined by the lowest value). The RPD/Vpp pin
provides an internal pulldown device that causes the external capacitor C2 to discharge at a
typical rate of 200 µA. Simply connecting two external capacitors, one to RSTIN pin and the
other to RPD/Vpp pin is sufficient for an automatic power-on reset. RSTIN may also be
connected to the output of other logic gates. When reset sequence is finished, the RPD/Vpp
capacitor will be charged by external pulldown or by internal pullup device if the bit
PWDCFG is set in SYSCON register.
1
RSTIN rising edge to internal latch of Port0 is 3 CPU clock cycles if the PLL is bypassed
and the prescaler is on (f
CPU
= f
XTAL
/ 2), else it is 4 CPU clock cycles
Figure 108 Asynchronous reset timing
CPU Clock
RSTIN
Internal
Reset Configuration
INST #1
PORT 0
RSTOUT
ALE
3 or 4 CPU clock 1)
RPD/Vpp
Asynchronous Reset Condition
Reset
Signal
Latching point of Port0
for system start-up configuration
