ST10R272L - GENERAL PURPOSE TIMER UNITS
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All three timers of block GPT1 (T2, T3, T4) can run in 3 basic modes: timer, gated timer, and
counter mode, and all timers can count either up or down. Each timer has an associated
alternate input function pin on Port 3, which serves as the gate control in gated timer mode,
or as the count input in counter mode. The count direction (Up / Down) can be programmed
by software or can be dynamically altered by a signal at an external control-input pin. Each
overflow/underflow of core timer T3 can be indicated on an alternate output function pin. The
auxiliary timers T2 and T4 can, additionally, be concatenated with the core timer, or used as
capture or reload registers for the core timer.
In incremental interface mode, the GPT1 timers (T2, T3, T4) can be directly connected to the
incremental position sensor signals A and B by their respective inputs TxIN and TxEUD.
Direction and count signals are internally derived from these two input signals - so the
contents of the respective timer Tx corresponds to the sensor position. The third position
sensor signal TOP0 can be connected to an interrupt input.
The current contents of each timer can be read or modified by the CPU by accessing the
corresponding timer registers T2, T3, or T4 located in the non-bitaddressable SFR space.
When any of the timer registers is written to by the CPU in the state immediately before a
timer increment, decrement, reload, or capture, the CPU write operation has priority. This is
to guarantee correct results.
Figure 69 GPT1 block diagram
2
n
n=3...10
2
n
n=3...10
2
n
n=3...10
T2EUD
T2IN
CPU Clock
CPU Clock
CPU Clock
T3IN
T4IN
T3EUD
T4EUD
T
2 Mode
Control
T
3 Mode
Control
T4
Mode
Control
GPT1 Timer T2
GPT1 Timer T3
GPT1 Timer T4
T3OTL
Reload
Capture
U/D
U/D
Reload
Capture
Interrupt
Request
Interrupt
Request
Interrupt
Request
T3OUT
U/D