ST10R272L - EXTERNAL BUS INTERFACE
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Should the ST10R272L require access to its external bus during hold mode, it activates its
bus request output BREQ to notify the arbitration circuitry. BREQ is activated only during
hold mode. It will be inactive during normal operation.
Note
The ST10R272L completes the running bus cycle before granting bus access,as
indicated by the broken lines. This may delay hold acknowledge compared to this
figure.
The figure above shows the first chance that BREQ has to become active.
9.6.2
Exiting the hold state
The external bus master returns the access rights to the ST10R272L by driving the HOLD
input high. After synchronizing this signal the ST10R272L will drive the HLDA output high,
actively drive the control signals and resume executing external bus cycles if required.
Depending on the arbitration logic, the external bus can be returned to the ST10R272L
under two circumstances:
•
The external master does no more require access to the shared resources and gives up
its own access rights, or
Figure 62 External bus arbitration - releasing the bus