ST10R272L - CENTRAL PROCESSING UNIT
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For the addition and subtraction with carry, the Z-flag is only set to ’1’ if the Z-flag already
contains a ’1’ and the result of the current ALU operation additionally equals zero. This
mechanism is provided for the support of multiple precision calculations.
For Boolean bit operations with only one operand, the Z-flag represents the logical negation
of the previous state of the specified bit. For Boolean bit operations with two operands, the
Z-flag represents the logical NORing of the two specified bits. For the prioritize ALU
operation the Z-flag indicates whether the second operand was zero or not.
E-Flag: The E-flag can be altered by instructions which perform ALU or data movement
operations. The E-flag is cleared by those instructions which cannot be, reasonably, used for
table search operations. In all other cases the E-flag is set by the value of the source
operand to signify whether the end of a search table is reached or not. If the value of the
source operand of an instruction equals the lowest negative number which is representable
by the data format of the corresponding instruction (’8000h’ for the word data-type, or ’80h’
for the byte data-type), the E-flag is set to ’1’, otherwise it is cleared.
MULIP-Flag: The MULIP-flag is be set to ’1’ by hardware on the entrance into an interrupt
service routine when a multiply or divide ALU operation is interrupted before completion.
Depending on the state of the MULIP bit, the hardware decides whether a multiplication or
division must be continued - or not, after the end of an interrupt service. The MULIP bit is
overwritten with the contents of the stacked MULIP-flag when the Return-From-Interrupt
instruction (RETI) is executed. This normally means that the MULIP-flag is cleared again
after that.
Note
The MULIP flag is a part of the task environment! When the interrupting service
routine does not return to the interrupted multiply/divide instruction (i.e. in case of a
task scheduler that switches between independent tasks), the MULIP flag must be
saved as part of the task environment and must be updated for the new task, before
this task is entered.
CPU interrupt status (IEN, ILVL)
The Interrupt Enable bit enables (IEN=’1’) or disables (IEN=’0’) interrupts. The four-bit
Interrupt Level field (ILVL) specifies the priority of the current CPU activity. The interrupt level
is updated by hardware on entry into an interrupt service routine, but it can also be modified
by software to prevent other interrupts from being acknowledged. An interrupt level of '15'
has the highest possible priority and the current CPU operation cannot be interrupted except
by hardware traps or external non-maskable interrupts. For details refer to “INTERRUPT
AND TRAP FUNCTIONS” on page 83.
After reset all interrupts are globally disabled and the lowest priority (ILVL=0) is assigned to
the initial CPU activity.
